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    Initial voltage generation circuit and method of generating an initial voltage
    1.
    发明授权
    Initial voltage generation circuit and method of generating an initial voltage 有权
    初始电压产生电路及产生初始电压的方法

    公开(公告)号：US09018932B2

    公开(公告)日：2015-04-28

    申请号：US13787837

    申请日：2013-03-07

    Applicant: Etron Technology, Inc.

    Inventor： Yen-An Chang ,  Yi-Hao Chang

    IPC: G05F1/00 ,  G06F3/02

    CPC classification number: G06F3/02 ,  G05F1/575 ,  G05F3/02

    Abstract: An initial voltage generation circuit includes a reference voltage generator, a reference voltage selector, at least one initial voltage level regulator, and a plurality of stabilization capacitors. The reference voltage generator generates a plurality of reference voltage candidate groups. The reference voltage selector includes a plurality of selection switch groups and a plurality of switch control circuits. Each selection switch group includes a plurality of parallel switches. Each switch control circuit corresponds to a selection switch group for generating a switch signal to control the selection switch group to output a reference voltage candidate of a corresponding reference voltage candidate group. Each initial voltage level regulator generates an inner reference voltage according to a power-up signal, and a stabilization capacitor corresponding to the initial voltage level regulator is used for stabilizing the inner reference voltage.

    Abstract translation: 初始电压产生电路包括参考电压发生器，参考电压选择器，至少一个初始电压电平调节器和多个稳定电容器。 参考电压发生器产生多个参考电压候选组。 参考电压选择器包括多个选择开关组和多个开关控制电路。 每个选择开关组包括多个并联开关。 每个开关控制电路对应于选择开关组，用于产生开关信号以控制选择开关组以输出相应参考电压候选组的参考电压候选。 每个初始电压电平调节器根据上电信号产生内部参考电压，并且使用与初始电压电平调节器相对应的稳定电容器来稳定内部参考电压。

    INPUT RECEIVER AND OPERATION METHOD THEREOF
    2.
    发明申请
    INPUT RECEIVER AND OPERATION METHOD THEREOF 有权
    输入接收器及其操作方法

    公开(公告)号：US20130234766A1

    公开(公告)日：2013-09-12

    申请号：US13789691

    申请日：2013-03-08

    Applicant: ETRON TECHNOLOGY, INC.

    Inventor： Yi-Hao Chang ,  Shih-Hsing Wang ,  Wen-Tung Yang ,  Yen-An Chang

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K19/0016

    Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.

    Abstract translation: 输入接收机包括第一输入接收单元，第二输入接收单元，延迟单元和第一逻辑单元。 第一输入接收单元接收反向唤醒信号，外部时钟使能信号，第一电压和参考信号，然后根据外部时钟使能信号和参考信号产生第一使能信号。 第二输入接收单元接收外部时钟使能信号，第一电压和反向使能电压，然后根据外部时钟使能信号产生第二使能信号作为其输出。 延迟单元根据第二使能信号产生唤醒信号。 第一逻辑单元接收唤醒信号和第一使能信号，然后根据唤醒信号和第一使能信号产生内部时钟使能信号。

    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
    3.
    发明公开
    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT 审中-公开

    公开(公告)号：US20240112707A1

    公开(公告)日：2024-04-04

    申请号：US18540888

    申请日：2023-12-15

    Applicant: Etron Technology, Inc

    Inventor： Der-Min Yuan ,  Yen-An Chang ,  Wei-Ming Huang

    IPC: G11C7/10 ,  G11C11/4074

    CPC classification number: G11C7/1075 ,  G11C11/4074 ,  G06F12/0882

    Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

    INITIAL VOLTAGE GENERATION CIRCUIT AND METHOD OF GENERATING AN INITIAL VOLTAGE
    4.
    发明申请
    INITIAL VOLTAGE GENERATION CIRCUIT AND METHOD OF GENERATING AN INITIAL VOLTAGE 有权
    初始电压发生电路及其初始电压产生方法

    公开(公告)号：US20130234694A1

    公开(公告)日：2013-09-12

    申请号：US13787837

    申请日：2013-03-07

    Applicant: ETRON TECHNOLOGY, INC.

    Inventor： Yen-An Chang ,  Yi-Hao Chang

    IPC: G05F3/02

    CPC classification number: G06F3/02 ,  G05F1/575 ,  G05F3/02

    Abstract: An initial voltage generation circuit includes a reference voltage generator, a reference voltage selector, at least one initial voltage level regulator, and a plurality of stabilization capacitors. The reference voltage generator generates a plurality of reference voltage candidate groups. The reference voltage selector includes a plurality of selection switch groups and a plurality of switch control circuits. Each selection switch group includes a plurality of parallel switches. Each switch control circuit corresponds to a selection switch group for generating a switch signal to control the selection switch group to output a reference voltage candidate of a corresponding reference voltage candidate group. Each initial voltage level regulator generates an inner reference voltage according to a power-up signal, and a stabilization capacitor corresponding to the initial voltage level regulator is used for stabilizing the inner reference voltage.

    Abstract translation: 初始电压产生电路包括参考电压发生器，参考电压选择器，至少一个初始电压电平调节器和多个稳定电容器。 参考电压发生器产生多个参考电压候选组。 参考电压选择器包括多个选择开关组和多个开关控制电路。 每个选择开关组包括多个并联开关。 每个开关控制电路对应于选择开关组，用于产生开关信号以控制选择开关组以输出相应参考电压候选组的参考电压候选。 每个初始电压电平调节器根据上电信号产生内部参考电压，并且使用与初始电压电平调节器相对应的稳定电容器来稳定内部参考电压。

    IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METHOD OF A LOW DROPOUT REGULATION SYSTEM
    5.
    发明申请
    IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METHOD OF A LOW DROPOUT REGULATION SYSTEM 有权
    立即应对低压差调节系统和低压差调节系统的操作方法

    公开(公告)号：US20130234684A1

    公开(公告)日：2013-09-12

    申请号：US13787823

    申请日：2013-03-07

    Applicant: ETRON TECHNOLOGY, INC.

    Inventor： Yen-An Chang ,  Kuang-Fu Teng ,  Der-Min Yuan

    IPC: G05F1/46

    CPC classification number: G05F1/468 ,  G05F1/575

    Abstract: An immediate response low dropout regulation system includes a low dropout regulation unit, a tracking voltage generation unit, and a self-driving unit. The low dropout regulation unit is used for generating and outputting an inner output voltage according to a reference voltage. The tracking voltage generation unit is used for generating and outputting a tracking voltage according to the reference voltage. The self-driving unit is coupled to the low dropout regulation unit and the tracking voltage generation unit. When a voltage difference between the tracking voltage and the inner output voltage is greater than a constant times threshold voltage, the self-driving unit provides a compensation current to an output terminal of the low dropout regulation unit.

    Abstract translation: 立即响应的低压差调节系统包括低压差调节单元，跟踪电压产生单元和自驱动单元。 低压差调节单元用于根据参考电压产生和输出内部输出电压。 跟踪电压产生单元用于根据参考电压产生和输出跟踪电压。 自驱动单元耦合到低压差调节单元和跟踪电压产生单元。 当跟踪电压和内部输出电压之间的电压差大于恒定时间阈值电压时，自驱动单元向低压差调节单元的输出端提供补偿电流。

    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
    7.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT 审中-公开

    公开(公告)号：US20190035440A1

    公开(公告)日：2019-01-31

    申请号：US16151347

    申请日：2018-10-04

    Applicant: Etron Technology, Inc.

    Inventor： Der-Min Yuan ,  Yen-An Chang ,  Wei-Ming Huang

    IPC: G11C7/10 ,  G11C11/4074

    Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

    MULTI-INPUT LOW DROPOUT REGULATOR
    8.
    发明申请
    MULTI-INPUT LOW DROPOUT REGULATOR 有权
    多输入低压差型稳压器

    公开(公告)号：US20140210438A1

    公开(公告)日：2014-07-31

    申请号：US14100009

    申请日：2013-12-08

    Applicant: Etron Technology, Inc.

    Inventor： Yen-An Chang ,  Yi-Hao Chang

    IPC: G05F1/56

    CPC classification number: G05F1/56 ,  G05F1/00 ,  G05F3/02

    Abstract: A multi-input low dropout regulator includes an amplifier, a first metal-oxide-semiconductor transistor, and a resistor. The amplifier has a plurality of first input terminals, a second input terminal, and an output terminal. Each first input terminal of the plurality of first input terminals is used for receiving an internal voltage. The first metal-oxide-semiconductor transistor has a first terminal for receiving a first voltage, a second terminal coupled to the output terminal of the amplifier, and a third terminal coupled the second input terminal of the amplifier. The resistor has a first terminal coupled to the third terminal of the first metal-oxide-semiconductor transistor, and a second terminal for receiving a second voltage. The third terminal of the first metal-oxide-semiconductor transistor is further used for coupling to a monitor pad, and the monitor pad is used for outputting the internal voltage.

    Abstract translation: 多输入低压差稳压器包括放大器，第一金属氧化物半导体晶体管和电阻器。 放大器具有多个第一输入端子，第二输入端子和输出端子。 多个第一输入端子的每个第一输入端用于接收内部电压。 第一金属氧化物半导体晶体管具有用于接收第一电压的第一端子，耦合到放大器的输出端子的第二端子和耦合放大器的第二输入端子的第三端子。 电阻器具有耦合到第一金属氧化物半导体晶体管的第三端子的第一端子和用于接收第二电压的第二端子。 第一金属氧化物半导体晶体管的第三端子还用于耦合到监视器焊盘，并且监视器焊盘用于输出内部电压。

    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
    10.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT 有权

    公开(公告)号：US20210217451A1

    公开(公告)日：2021-07-15

    申请号：US17213133

    申请日：2021-03-25

    Applicant: Etron Technology, Inc.

    Inventor： Der-Min Yuan ,  Yen-An Chang ,  Wei-Ming Huang

    IPC: G11C7/10 ,  G11C11/4074

    Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

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