摘要:
A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.
摘要:
A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.
摘要:
A method for increasing data rate in wireless communications includes selectively activating a plurality of hardware accelerators, and performing, using the hardware accelerators, data processing for modem data based on parameters received from a processor.
摘要:
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
摘要:
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
摘要:
A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
摘要:
A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.
摘要:
A Node-B/base station has an access burst detector. The access burst detector comprises at least one antenna for receiving signals from users and a pool of reconfigurable correlators. Each correlator correlates an inputted access burst code at an inputted code phase with an inputted antenna output. An antenna controller selectively couples any output of the at least one antenna to an input of any of the correlators. A code controller provides to an input of each correlator an access burst code. The code controller controls the inputted code phase of each controller. A sorter/post processor sorts output energy levels of the correlators.
摘要:
Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.
摘要:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.