Predicting Wafer Failure Using Learned Probability
    5.
    发明申请
    Predicting Wafer Failure Using Learned Probability 有权
    使用学习概率预测晶圆失效

    公开(公告)号:US20100145646A1

    公开(公告)日:2010-06-10

    申请号:US12329868

    申请日:2008-12-08

    IPC分类号: G06F19/00

    摘要: Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

    摘要翻译: 提出了用于估计一个或多个晶片的质量的技术。 测试包括一个或多个第一裸片的一个或多个第一晶片。 根据一个或多个第一模具的一个或多个第一测试测量值确定晶片故障的概率。 通过测试一个或多个第二晶片的选择的一个或多个第二管芯并且评估所选择的一个或多个第二管芯的一个或多个第二测试测量结果来推断一个或多个第二晶片的通过状态和/或失败状态 根据确定的晶圆故障概率。

    Predicting wafer failure using learned probability
    6.
    发明授权
    Predicting wafer failure using learned probability 有权
    使用学习概率预测晶圆故障

    公开(公告)号:US07962302B2

    公开(公告)日:2011-06-14

    申请号:US12329868

    申请日:2008-12-08

    IPC分类号: G06F19/00

    摘要: Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure.

    摘要翻译: 提出了用于估计一个或多个晶片的质量的技术。 测试包括一个或多个第一裸片的一个或多个第一晶片。 根据一个或多个第一模具的一个或多个第一测试测量值确定晶片故障的概率。 通过测试一个或多个第二晶片的选择的一个或多个第二管芯并且评估所选择的一个或多个第二管芯的一个或多个第二测试测量结果来推断一个或多个第二晶片的通过状态和/或失败状态 根据确定的晶圆故障概率。