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25 条记录 (耗时 0.039 秒)

    Method and system for integrated circuit design
    5.
    发明授权
    Method and system for integrated circuit design 失效
    集成电路设计方法与系统

    公开(公告)号：US06865725B2

    公开(公告)日：2005-03-08

    申请号：US10249639

    申请日：2003-04-28

    申请人： Carl E. Dickey ,  Donald L. Jordan ,  Raminderpal Singh ,  Sue E. Strang

    发明人： Carl E. Dickey ,  Donald L. Jordan ,  Raminderpal Singh ,  Sue E. Strang

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5077

    摘要： A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.

    摘要翻译： 一种用于设计集成电路的方法，包括：基于分区准则划分集成电路设计的互连以创建一组互连分区; 从在每组互连分区的互连上执行的一组分析方法中选择至少一种分析方法; 以及在每个对应的互连分区的互连上执行每个选择的分析方法。

    On chip resistor calibration structure and method
    6.
    发明授权
    On chip resistor calibration structure and method 失效
    片上电阻校准结构及方法

    公开(公告)号：US06825490B1

    公开(公告)日：2004-11-30

    申请号：US10605567

    申请日：2003-10-09

    申请人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

    发明人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

    IPC分类号： H01L2358

    CPC分类号： G01R35/005

    摘要： A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.

    摘要翻译： 确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。 半导体器件包括电容器，校准电阻器和校准电路。 施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。 校准电路适于测量对电容器充电所需的实际时间。 校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。

    Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction
    9.
    发明授权
    Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效
    使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法

    公开(公告)号：US07139990B2

    公开(公告)日：2006-11-21

    申请号：US10807478

    申请日：2004-03-23

    申请人： Raminderpal Singh ,  Yue Tan ,  Jean-Oliver Plouchart ,  Lawrence F. Wagner, Jr. ,  Mohamed Talbi ,  John M. Safran ,  Kun Wu

    发明人： Raminderpal Singh ,  Yue Tan ,  Jean-Oliver Plouchart ,  Lawrence F. Wagner, Jr. ,  Mohamed Talbi ,  John M. Safran ,  Kun Wu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5022

    摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

    摘要翻译： 描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。 通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。 通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。 这种完整和准确的几何参数比较增强了布局物理验证的置信度。

    Method for designing an integrated circuit having multiple voltage domains
    10.
    发明授权
    Method for designing an integrated circuit having multiple voltage domains 失效
    用于设计具有多个电压域的集成电路的方法

    公开(公告)号：US07000214B2

    公开(公告)日：2006-02-14

    申请号：US10707068

    申请日：2003-11-19

    申请人： Joseph A. Iadanza ,  Raminderpal Singh ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    发明人： Joseph A. Iadanza ,  Raminderpal Singh ,  Sebastian T. Ventrone ,  Ivan L. Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

    摘要翻译： 一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。