-
公开(公告)号：US20050270119A1
公开(公告)日：2005-12-08
申请号：US11143632
申请日：2005-06-03
IPC分类号： H01P1/15 , H03K17/693
CPC分类号： H03K17/693
摘要： A semiconductor apparatus is provided which makes it possible to reduce the number of control terminals required for switching through paths of a high frequency signal, simplify the circuit configuration for controlling the terminals, improve an isolation characteristic between on path and off path of a through FET, and obtain a sufficiently high isolation. In this semiconductor apparatus, one specific through FET and each of shunt FETs connected to each of through FETs other than the one specific through FET are simultaneously turned on in response to the same control signal inputted to the same control terminal. Thus, when a high frequency signal leaks from an output terminal to the signal path of the through FET having been turned on, through the signal paths of the through FETs having been turned off, the high frequency signal can be released to GND through the shunt FET having been turned on.
摘要翻译： 提供一种半导体装置，其可以减少切换高频信号的路径所需的控制端子的数量，简化用于控制端子的电路结构，提高通过FET的通路和截止路径之间的隔离特性 ，并获得足够高的隔离度。 在该半导体装置中，响应于输入到同一控制端子的相同的控制信号，一个特定的通过FET和连接到除一个特定通孔之外的每个通孔的分流FET同时导通。 因此，当高频信号从已经导通的通过FET的输出端子泄漏到通过FET的信号路径时，通过截止的通过FET的信号路径，高频信号可以通过分流器被释放到GND FET已经接通。
-
公开(公告)号：US06871058B2
公开(公告)日：2005-03-22
申请号：US10114029
申请日：2002-04-03
申请人： Haruhiko Koizumi , Katsushi Tara
发明人： Haruhiko Koizumi , Katsushi Tara
CPC分类号： H03D7/125
摘要： The present invention provides a frequency conversion circuit capable of reducing current without impairing high frequency characteristics. A local oscillator amplifier is formed of a first field effect transistor. A source thereof is grounded by a first capacitor in terms of high frequency, and a gate thereof is connected to one end of each of first and second resistors. The other end of the first resistor is grounded, and the other end of the second resistor is connected to a voltage supply terminal. An intermediate frequency amplifier is formed of a second field effect transistor. A source thereof is grounded through a third resistor and a second capacitor that are connected in parallel with each other. A drain thereof is connected to an intermediate frequency signal output terminal through a third capacitor and an intermediate frequency output matching circuit. The source of the first field effect transistor and the drain of the second field effect transistor are connected through an AC blocking circuit.
摘要翻译： 本发明提供一种能够在不损害高频特性的情况下降低电流的频率变换电路。 本地振荡器放大器由第一场效应晶体管形成。 其源极以高频率由第一电容器接地，并且其栅极连接到第一和第二电阻器的每一个的一端。 第一电阻的另一端接地，第二电阻的另一端连接到电源端。 中频放大器由第二场效应晶体管形成。 其源极通过彼此并联连接的第三电阻器和第二电容器接地。 其漏极通过第三电容器和中频输出匹配电路连接到中频信号输出端子。 第一场效应晶体管的源极和第二场效应晶体管的漏极通过AC阻断电路连接。
-
公开(公告)号：US06229370B1
公开(公告)日：2001-05-08
申请号：US09446626
申请日：2000-05-12
IPC分类号： H03L500
CPC分类号： H03G1/007 , H03H11/245 , H03K2217/0054
摘要： To achieve linear gain control (with a flatness of ±1 dB) over a wide range of 70 dB or greater using a single control voltage in a high frequency section of a mobile terminal transmitter, a signal input part 34 and a signal output part 35 are connected by a signal line 51 containing at least two series variable resistors 51 and 52, parallel variable resistors 53 and 54 are connected between a ground line 57 and the signal input part 34 and signal output part 35, respectively, a gain control line 56 is connected to the variable resistors 51, 52, 53, and 54, reference voltage application parts 23, 27, 31, and 33 are connected to the variable resistors 51, 52, 53, and 54, respectively, and a gain control voltage application part 19 is connected to the variable resistors 51, 52, 53, and 54 via the gain control line 56.
摘要翻译： 为了在移动终端发射机的高频部分中使用单个控制电压，在70dB或更大的宽范围内实现线性增益控制（平坦度为±1dB），信号输入部分34和信号输出部分35 通过包含至少两个串联可变电阻器51和52的信号线51连接，并联可变电阻器53和54分别连接在接地线57和信号输入部分34和信号输出部分35之间，增益控制线56 连接到可变电阻器51,52,53和54，参考电压施加部件23,27,31和33分别连接到可变电阻器51,52,53和54，并且增益控制电压施加 部分19通过增益控制线56连接到可变电阻器51,52,53和54。
-
4.发明授权公开(公告)号：US08193091B2
公开(公告)日：2012-06-05
申请号：US10173900
申请日：2002-06-19
申请人： Fumihiko Kawai , Toshiyuki Fukuda , Masanori Minamio , Noboru Takeuchi , Shuichi Ogata , Katsushi Tara , Tadayoshi Nakatsuka
发明人： Fumihiko Kawai , Toshiyuki Fukuda , Masanori Minamio , Noboru Takeuchi , Shuichi Ogata , Katsushi Tara , Tadayoshi Nakatsuka
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L21/4842 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06179 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48471 , H01L2224/49111 , H01L2224/49113 , H01L2224/4912 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/73265 , H01L2224/85191 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/10161 , H01L2924/10329 , H01L2924/181 , H01L2924/18301 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/48227 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015 , H01L2224/05599 , H01L2224/4554
摘要： The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.
摘要翻译： 本发明包括一个管芯焊盘; 信号引线，接地连接引线连接到管芯焊盘; 包括用于接地的电极焊盘的半导体芯片; 金属细线，以及用于封装芯片焊盘和半导体芯片的封装树脂，并封装信号引线和接地连接引线，使得信号引线和接地连接引线的下部被暴露为外部端子。 接地连接引线连接到电极焊盘用于接地，使得树脂封装的半导体器件电稳定。 此外，可以通过管芯焊盘和接地连接引线来抑制通过信号引线的高频信号之间的干扰。
-
公开(公告)号：US07276975B2
公开(公告)日：2007-10-02
申请号：US11194465
申请日：2005-08-02
申请人： Kazuki Tateoka , Katsushi Tara , Kaname Motoyoshi
发明人： Kazuki Tateoka , Katsushi Tara , Kaname Motoyoshi
IPC分类号： H03F3/191
摘要： A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding transistor, and inductors L11 through L1n having one end commonly connected to a DC power supply input terminal DCin and the other end connected to a base electrode of a corresponding transistor, RF noise generated in a DC power supply circuit is reduced. This can reduce the RF noise output from the transistors Tr11 through Tr1n. The inductors L11 through L1n prevent an RF signal input from the RF input terminal RFin from flowing toward the DC power supply circuit. This can prevent the RF signal from being lost by the flow thereof toward the DC power supply circuit.
摘要翻译： 提供了具有极好的RF特性并防止晶体管的热失控的产生较少噪声的晶体管集成电路装置。 由于电容器C 11至C 1 n的一端共同地连接到RF信号输入端RFin并且另一端连接到相应晶体管的基极，并且电感器L 11至L 1 n具有一端共同连接到 直流电源输入端子DCin，另一端连接到相应晶体管的基极，降低了在直流电源电路中产生的RF噪声。 这可以减少从晶体管Tr 11至Tr 1 n输出的RF噪声。 电感器L 11〜L 1 n防止从RF输入端子RFin输入的RF信号流向直流电源电路。 这可以防止RF信号流向DC电源电路而流失。
-
公开(公告)号：US07199635B2
公开(公告)日：2007-04-03
申请号：US10864352
申请日：2004-06-10
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
-
公开(公告)号：US07173471B2
公开(公告)日：2007-02-06
申请号：US10864351
申请日：2004-06-10
申请人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
发明人： Tadayoshi Nakatsuka , Atsushi Suwa , Katsushi Tara
IPC分类号： H03L5/00
CPC分类号： H03K17/04123 , H03K17/693
摘要： Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
摘要翻译： 在串联连接的四个FET组成的四个开关电路部分设置在输出并输入高频信号的多个输入/输出端子之间。 栅极控制电压分别分别施加到四个FET的栅极端子，从而实现导通状态和截止状态。 在各开关电路部分中分别对漏极端子或FET的源极施加进一步的漏极控制电压，并且提供根据提供给每个开关电路部分的高频信号的电功率值的电压作为栅极控制电压 和漏极控制电压。
-
公开(公告)号：US20060001473A1
公开(公告)日：2006-01-05
申请号：US11169314
申请日：2005-06-29
申请人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
发明人： Eiji Yasuda , Kenichi Hidaka , Yasuyuki Masumoto , Tadayoshi Nakatsuka , Atsushi Watanabe , Katsushi Tara
IPC分类号： H03K17/62
CPC分类号： H03K17/693
摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.
摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。
-
公开(公告)号：US07636004B2
公开(公告)日：2009-12-22
申请号：US11672415
申请日：2007-02-07
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
-
公开(公告)号：US20060181328A1
公开(公告)日：2006-08-17
申请号：US11402849
申请日：2006-04-13
IPC分类号： H03K17/693
CPC分类号： H03K17/102 , H03K17/6871 , H03K17/693 , H03K2217/0036
摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.028 秒)
