公开(公告)号：US20140266354A1

公开(公告)日：2014-09-18

申请号：US14028707

申请日：2013-09-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyun Ho BOO ,  Byung Hun MIN ,  Duong Quoc HOANG ,  Cheon Soo KIM ,  Hyun Kyu YU

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/095

Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

Abstract translation: 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。

公开(公告)号：US20140169512A1

公开(公告)日：2014-06-19

申请号：US14183513

申请日：2014-02-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jung Woo PARK ,  Young Jae LEE ,  Hyun Kyu Yu ,  Byung Hun MIN ,  Seong Do KIM ,  Hoai Nam NGUYEN ,  Sang Gug LEE

IPC: H04L25/08

CPC classification number: H04L25/08 ,  H03D7/1441 ,  H03D7/1458 ,  H03H19/004

Abstract: A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

Abstract translation: 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。