STRETCHABLE DISPLAY DEVICE
    4.
    发明申请

    公开(公告)号:US20210280827A1

    公开(公告)日:2021-09-09

    申请号:US17191276

    申请日:2021-03-03

    IPC分类号: H01L51/52 H01L51/00

    摘要: Provided is a stretchable display device. The stretchable display device includes a substrate and a base pattern on the substrate, wherein the base pattern comprises a first portion, a second portion, and a connection portion configured to connect the first portion to the second portion. The stretchable display device includes a lower electrode on the first portion of the base pattern; an upper electrode on the lower electrode, a light emitting structure between the lower electrode and the upper electrode, and a protective layer configured to cover top and side surfaces of the upper electrode, side surfaces of the light emitting structure, a side surface of the lower electrode, and a portion of a side surface of the base pattern. The upper electrode extends to a top surface of the connection portion and a top surface of the second portion of the base pattern, and the first portion and the second portion of the base pattern extend in a first direction parallel to a top surface of the substrate. The first portion and the second portion are parallel to the top surface of the substrate and are spaced apart from each other in a second direction crossing the first direction.
    The connection portion extends in the second direction. A level of the lowermost surface of the protective layer is disposed between a bottom surface of the lower electrode and a bottom surface of the base pattern.

    PIXEL CIRCUIT FOR CONFIGURING ACTIVE INPUT ARRAY AND INPUT DEVICE INCLUDING THE SAME

    公开(公告)号:US20200072665A1

    公开(公告)日:2020-03-05

    申请号:US16552550

    申请日:2019-08-27

    IPC分类号: G01J1/46 G06F3/01 G01L9/08

    摘要: Provided is a pixel circuit. The pixel circuit includes a conversion element configured to form a voltage of an input level corresponding to a magnitude of a received energy at a first node, a first transistor configured to adjust the voltage of the first node to a first level in response to a first signal received at a first time interval, a first capacitive element configured to form a voltage at a second node based on the voltage of the first node, a second transistor configured to adjust a level of the voltage of the second node to a second level in response to the first signal, a third transistor configured to form a voltage at a third node, the voltage having a level corresponding to the level of the voltage of the second node, a fourth transistor configured to output a current corresponding to the voltage of the third node in response to a second signal received in a second time interval after the first time interval, and a fifth transistor configured to adjust the voltage of the third node to a third level in response to a third signal received in a third time interval after the second time interval.