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公开(公告)号：US11382244B2
公开(公告)日：2022-07-05
申请号：US16566221
申请日：2019-09-10
Inventor： Seong Jun Kim , Choon Gi Choi , Tam Van Nguyen , Bok Ki Min , Shuvra Mondal , Yoonsik Yi
Abstract: Provided is a temperature-pressure complex sensor with an anti-radiation property including a first sensing material which is a porous conductive film, and second sensing materials which are dispersedly disposed on a surface of the first sensing material. The second sensing materials may include a conductive structure having a two-dimensional crystal structure, and nanoparticles having a radiation shielding property which are disposed between crystal layers of the conductive structure.
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公开(公告)号：US11828718B2
公开(公告)日：2023-11-28
申请号：US17314038
申请日：2021-05-06
Inventor： Choon Gi Choi , Mondal Shuvra , Bok Ki Min , Yoonsik Yi
CPC classification number: G01N27/121 , G01K7/02 , G01K7/16 , H01H13/04 , H01H13/70
Abstract: Provided is a button device including a humidity sensor. The button device includes a substrate having a plurality of sensing regions, a housing on the substrate, the housing separating a first sensing region of the plurality of sensing regions from other sensing regions, a porous structure within the housing, the porous structure having through-holes, a first electrode on the porous structure, a second electrode on the porous structure, the second electrode being electrically connected to the first electrode through the porous structure, and a temperature sensor disposed adjacent to the first sensing region to sense a temperature of the first sensing region, The porous structure includes a body having an outer surface defining the through-holes, the body having an air gap therein.
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公开(公告)号：US20250070089A1
公开(公告)日：2025-02-27
申请号：US18750090
申请日：2024-06-21
Inventor： Yong Suk Yang , Myung Lae Lee , Jengsu Yoo , Yoonsik Yi
IPC: H01L25/065 , H01L25/00
Abstract: Provided are a 3-dimensional electronic device and a method for manufacturing the 3-dimensional electronic device. The method includes coupling semiconductor chips and guide blocks onto a substrate, forming an upper mold layer and upper wires on the semiconductor chips and the guide blocks by using a 3D printing method, stacking substrates other than the substrate on the upper mold layer and the upper wires, sawing a portion of each of the guide blocks and the upper mold layer, and forming a side mold layer and side wires on sidewalls of via electrodes of the guide blocks by using the 3D printing method.
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