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    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
    2.
    发明授权
    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
    采用介质存储元件的多状态非易失性集成电路存储器系统

    公开(公告)号：US07579247B2

    公开(公告)日：2009-08-25

    申请号：US12020296

    申请日：2008-01-25

    申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

    摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

    摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
    4.
    发明授权
    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
    采用介质存储元件的多状态非易失性集成电路存储器系统

    公开(公告)号：US07834392B2

    公开(公告)日：2010-11-16

    申请号：US12510077

    申请日：2009-07-27

    申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

    摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

    摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
    5.
    发明授权
    Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
    采用介质存储元件的多状态非易失性集成电路存储器系统

    公开(公告)号：US07341918B2

    公开(公告)日：2008-03-11

    申请号：US11075427

    申请日：2005-03-07

    申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

    IPC分类号： H01L21/467 ,  H01L21/8239

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

    摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

    摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

    Steering gate and bit line segmentation in non-volatile memories
    7.
    发明授权
    Steering gate and bit line segmentation in non-volatile memories 有权
    非易失性存储器中的转向门和位线分割

    公开(公告)号：US06532172B2

    公开(公告)日：2003-03-11

    申请号：US09871333

    申请日：2001-05-31

    申请人： Eliyahou Harari ,  George Samachisa ,  Daniel C. Guterman ,  Jack H. Yuan

    发明人： Eliyahou Harari ,  George Samachisa ,  Daniel C. Guterman ,  Jack H. Yuan

    IPC分类号： G11C1604

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491

    摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

    摘要翻译： 转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。 在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。 包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。 这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理较高电压的晶体管。 在另一个实施例中，组合本地导向门线段以便减少它们的数量，然后每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择 该段。

    Dual floating gate EEPROM cell array with steering gates shared adjacent cells
    8.
    发明授权
    Dual floating gate EEPROM cell array with steering gates shared adjacent cells 有权
    具有转向门的双浮栅EEPROM单元阵列共享相邻单元

    公开(公告)号：US06266278B1

    公开(公告)日：2001-07-24

    申请号：US09634694

    申请日：2000-08-08

    申请人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

    发明人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

    IPC分类号： G11C1604

    CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L27/115

    摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.

    摘要翻译： 具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。 双门单元增加了可以存储的数据的密度。 不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。 因此，转向门由不同但相邻的存储单元的两个浮动门共享。 在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为 增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。 在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。 单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度 存储。 多个数据位也可以存储在每个浮动门上。