公开(公告)号：US20080109639A1

公开(公告)日：2008-05-08

申请号：US11592337

申请日：2006-11-03

申请人： Elodie Charra ,  Frederic Claude Marie Piry ,  Richard Roy Grisenthwaite ,  Melanie Emanuelle Lucie Vincent ,  Norbert Bernard Eugene Lataille ,  Jocelyn Francois Orion Jaubert ,  Stuart David Biles

发明人： Elodie Charra ,  Frederic Claude Marie Piry ,  Richard Roy Grisenthwaite ,  Melanie Emanuelle Lucie Vincent ,  Norbert Bernard Eugene Lataille ,  Jocelyn Francois Orion Jaubert ,  Stuart David Biles

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F15/8007 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/3897 ,  G06F12/0837

摘要： A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster. Such a mechanism provides a particularly efficient technique to cause each of the processing units in the cluster to perform an identical operation which can be useful in a variety of situations, for example in an SMP system where coherency of data is required and accordingly maintenance operations need to be performed periodically within each processing unit to ensure such coherency.

摘要翻译： 提供了一种用于处理具有多个处理单元的数据处理装置内的指令执行的数据处理装置和方法。 每个处理单元可操作以执行指令序列，以便执行相关联的操作，并且处理单元的至少一个子集形成一个簇。 提供了指令转发逻辑，对于由集群中的至少一个处理单元执行的至少一个指令，导致该指令由集群中的每个其他处理单元执行，例如通过使该指令被插入 由群集中的每个其他处理单元执行的指令序列。 这样的机制提供了一种特别有效的技术，以使群集中的每个处理单元执行相同的操作，其可以在各种情况下有用，例如在需要数据的一致性并因此需要维护操作的SMP系统中 以在每个处理单元内周期性地执行以确保这样的一致性。

公开(公告)号：US20080148022A1

公开(公告)日：2008-06-19

申请号：US11637947

申请日：2006-12-13

申请人： Frederic Claude Marie Piry ,  Melanie Emanuelle Lucie Vincent ,  Florent Begon ,  Gilles Eric Grandou ,  Norbert Bernard Eugene Lataille

发明人： Frederic Claude Marie Piry ,  Melanie Emanuelle Lucie Vincent ,  Florent Begon ,  Gilles Eric Grandou ,  Norbert Bernard Eugene Lataille

IPC分类号： G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/384 ,  G06F9/3863

摘要： The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second data store for storing a recovery renaming table, said recovery renaming table comprising a most recently committed mapping of said processor; wherein said register renaming circuitry is responsive to detection of a predetermined condition to mark said physical registers not mapped in said recovery renaming table as available for renaming.

摘要翻译： 本申请公开了一种用于将寄存器从体系结构寄存器映射到物理寄存器组内的寄存器的寄存器重命名电路，所述寄存器结构集是由指令集内的指令指定的寄存器，所述物理寄存器组是处理器内的寄存器 用于处理所述指令集的指令，所述指令集包括异常指令和非异常指令，异常指令是可以产生异常的指令，非异常指令是以静态可确定的方式执行的指令，所述寄存器重命名电路包括： 用于存储未来重命名表的第一数据存储器，所述未来重命名表包括将用于将寄存器映射到所述体系结构寄存器的值的值重命名为所述物理寄存器组中的寄存器，用于将由sai执行或正在执行的指令 d处理器 用于存储恢复重命名表的第二数据存储器，所述恢复重命名表包括所述处理器的最近提交的映射; 其中所述寄存器重命名电路响应于预定条件的检测，以将未映射在所述恢复重命名表中的所述物理寄存器标记为可用于重命名。

公开(公告)号：US20080082792A1

公开(公告)日：2008-04-03

申请号：US11892295

申请日：2007-08-21

申请人： Melanie Emanuelle Lucie Vincent ,  Forent Begon ,  Cedric Denis Robert Airaud ,  Norbert Bernard Eugene Lataille

发明人： Melanie Emanuelle Lucie Vincent ,  Forent Begon ,  Cedric Denis Robert Airaud ,  Norbert Bernard Eugene Lataille

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

摘要翻译： 利用寄存器重命名的处理器2执行需要通过将重命名任务划分为初始集合和剩余集合来重命名大量架构寄存器说明符的程序指令。 首先执行初始设置，并且结果通过主通道32进行进一步处理。 依次执行剩余集合，结果通过背景通道34进行进一步处理。 这种技术对于执行加载/存储多个LDM指令的重命名操作特别有用。

公开(公告)号：US07698537B2

公开(公告)日：2010-04-13

申请号：US11641959

申请日：2006-12-20

申请人： Cédric Denis Robert Airaud ,  Melanie Emanuelle Lucie Vincent ,  Luc Orion ,  Norbert Bernard Eugene Lataille

发明人： Cédric Denis Robert Airaud ,  Melanie Emanuelle Lucie Vincent ,  Luc Orion ,  Norbert Bernard Eugene Lataille

IPC分类号： G06F9/00

CPC分类号： G06F9/4812 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885 ,  G06F2209/481

摘要： A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming. Control circuitry identifies exception instructions in the instruction stream and detects when the exception instructions have been committed. The second processing block receives signals from the control circuitry and suspends processing of an instruction in the second processing block until all preceding exception instructions have been committed.

摘要翻译： 数据处理装置处理来自指令集的指令流。 指令集包括异常指令和非异常指令。 异常指令可能导致指令流中断，非异常指令以静态可确定的方式执行。 至少两个处理块处理来自指令流的指令。 第一处理块具有与其相关联的一组物理寄存器，用于存储由第一处理块正在处理的数据值。 与第一处理块相关联的重命名电路将由第一处理块处理的指令中指定的体系结构寄存器映射到物理寄存器组内的物理寄存器。 第二处理块具有与其相关联的一组物理寄存器，用于存储由第二处理块正在处理的数据值。 第二个处理块和寄存器不支持重命名。 控制电路识别指令流中的异常指令，并检测何时提交异常指令。 第二处理块从控制电路接收信号并暂停对第二处理块中的指令的处理，直到所有先前的异常指令都被提交。

公开(公告)号：US07844800B2

公开(公告)日：2010-11-30

申请号：US11892295

申请日：2007-08-21

申请人： Melanie Emanuelle Lucie Vincent ,  Florent Begon ,  Cedric Denis Robert Airaud ,  Norbert Bernard Eugene Lataille

发明人： Melanie Emanuelle Lucie Vincent ,  Florent Begon ,  Cedric Denis Robert Airaud ,  Norbert Bernard Eugene Lataille

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

摘要翻译： 利用寄存器重命名的处理器2执行需要通过将重命名任务划分为初始集合和剩余集合来重命名大量架构寄存器说明符的程序指令。 首先执行初始设置，并且结果通过主通道32进行进一步处理。 依次执行剩余集合，结果通过背景通道34进行进一步处理。 这种技术对于执行加载/存储多个LDM指令的重命名操作特别有用。

公开(公告)号：US20080155238A1

公开(公告)日：2008-06-26

申请号：US11641959

申请日：2006-12-20

申请人： Cedric Denis Robert Airaud ,  Melanie Emanuelle Lucie Vincent ,  Luc Orion ,  Norbert Bernard Eugene Lataille

发明人： Cedric Denis Robert Airaud ,  Melanie Emanuelle Lucie Vincent ,  Luc Orion ,  Norbert Bernard Eugene Lataille

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885 ,  G06F2209/481

摘要： A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said data processing apparatus comprising: at least two processing blocks for processing instructions from said stream of instructions; a first processing block having a set of physical registers associated with it for storing data values being processed by said first processing block, renaming circuitry associated with said first processing block for mapping architectural registers specified in instructions to be processed by said first processing block to physical registers within said set of physical registers; a second processing block having a set of physical registers associated with it for storing data values being processed by said second processing block, said second processing block and registers not supporting renaming; control circuitry configured to identify exception instructions in said instruction stream and to detect when said exception instructions have been committed; said second processing block being configured to receive signals from said control circuitry and to suspend processing of an instruction in said second processing block until all preceding exception instructions have been committed.

摘要翻译： 一种数据处理装置，可操作以处理来自指令集的指令流，所述指令集包括异常指令和非异常指令，异常指令是可能导致指令流中断的指令，非异常指令是执行的指令 所述数据处理装置包括：用于处理来自所述指令流的指令的至少两个处理块; 第一处理块，具有与其相关联的一组物理寄存器，用于存储由所述第一处理块处理的数据值，将与所述第一处理块相关联的重命名电路重新命名，用于将由所述第一处理块处理的指令中指定的架构寄存器映射到物理 在所述一组物理寄存器内寄存器; 第二处理块，具有与其相关联的一组物理寄存器，用于存储由所述第二处理块正在处理的数据值，所述第二处理块和不支持重命名的寄存器; 控制电路，被配置为识别所述指令流中的异常指令，并检测所述异常指令何时已被提交; 所述第二处理块被配置为从所述控制电路接收信号并暂停所述第二处理块中的指令的处理，直到所有先前的异常指令都被提交。