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1.发明授权Method for renaming a large number of registers in a data processing system using a background channel 有权使用背景通道在数据处理系统中重命名大量寄存器的方法公开(公告)号：US07844800B2
公开(公告)日：2010-11-30
申请号：US11892295
申请日：2007-08-21
申请人： Melanie Emanuelle Lucie Vincent , Florent Begon , Cedric Denis Robert Airaud , Norbert Bernard Eugene Lataille
发明人： Melanie Emanuelle Lucie Vincent , Florent Begon , Cedric Denis Robert Airaud , Norbert Bernard Eugene Lataille
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.
摘要翻译： 利用寄存器重命名的处理器2执行需要通过将重命名任务划分为初始集合和剩余集合来重命名大量架构寄存器说明符的程序指令。 首先执行初始设置，并且结果通过主通道32进行进一步处理。 依次执行剩余集合，结果通过背景通道34进行进一步处理。 这种技术对于执行加载/存储多个LDM指令的重命名操作特别有用。
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公开(公告)号：US20080148022A1
公开(公告)日：2008-06-19
申请号：US11637947
申请日：2006-12-13
申请人： Frederic Claude Marie Piry , Melanie Emanuelle Lucie Vincent , Florent Begon , Gilles Eric Grandou , Norbert Bernard Eugene Lataille
发明人： Frederic Claude Marie Piry , Melanie Emanuelle Lucie Vincent , Florent Begon , Gilles Eric Grandou , Norbert Bernard Eugene Lataille
IPC分类号： G06F15/00
CPC分类号： G06F9/3842 , G06F9/384 , G06F9/3863
摘要： The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second data store for storing a recovery renaming table, said recovery renaming table comprising a most recently committed mapping of said processor; wherein said register renaming circuitry is responsive to detection of a predetermined condition to mark said physical registers not mapped in said recovery renaming table as available for renaming.
摘要翻译： 本申请公开了一种用于将寄存器从体系结构寄存器映射到物理寄存器组内的寄存器的寄存器重命名电路，所述寄存器结构集是由指令集内的指令指定的寄存器，所述物理寄存器组是处理器内的寄存器 用于处理所述指令集的指令，所述指令集包括异常指令和非异常指令，异常指令是可以产生异常的指令，非异常指令是以静态可确定的方式执行的指令，所述寄存器重命名电路包括： 用于存储未来重命名表的第一数据存储器，所述未来重命名表包括将用于将寄存器映射到所述体系结构寄存器的值的值重命名为所述物理寄存器组中的寄存器，用于将由sai执行或正在执行的指令 d处理器 用于存储恢复重命名表的第二数据存储器，所述恢复重命名表包括所述处理器的最近提交的映射; 其中所述寄存器重命名电路响应于预定条件的检测，以将未映射在所述恢复重命名表中的所述物理寄存器标记为可用于重命名。
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3.发明申请Suppressing register renaming for conditional instructions predicted as not executed 有权对预测为未执行的条件指令抑制寄存器重命名公开(公告)号：US20080177984A1
公开(公告)日：2008-07-24
申请号：US11657135
申请日：2007-01-24
IPC分类号： G06F9/00
CPC分类号： G06F9/30072 , G06F9/30043 , G06F9/384
摘要： Within a data processing system 2 including a register renaming mechanism 8, 22, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers 24 if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to signal instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.
摘要翻译： 在包括寄存器重命名机制8,22的数据处理系统2中，抑制了预测为未执行的一些条件指令的寄存器重命名。 受到这种抑制重命名的条件指令可能不是全部条件指令，但是可以是已知消耗特定数量的物理寄存器24的条件指令，如果它们被重命名为有条件加载多指令，其中多个寄存器 加载了响应于信号指令从存储器获取的新的数据值是可以使用本技术的示例，特别是当加载的一个寄存器是程序计数器并且因此该指令是条件分支时。
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公开(公告)号：US07624253B2
公开(公告)日：2009-11-24
申请号：US11586007
申请日：2006-10-25
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/384 , G06F9/3863
摘要： A data processing apparatus 2 supports out-of-order processing register renaming using a renaming stage 8. A set of physical registers 16 is mapped to architectural registers. Available-register identifying logic 26 is used to identify which physical registers 16 are available for use by the renaming stage 8. The available-register identifying logic 26 includes an instruction FIFO 28 storing register mapping data for unresolved instructions and indicating physical registers 16 storing data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.
摘要翻译： 数据处理装置2支持使用重命名级8的无序处理寄存器重命名。一组物理寄存器16映射到架构寄存器。 可用寄存器识别逻辑26用于识别哪些物理寄存器16可用于重命名级8.可用寄存器识别逻辑26包括指令FIFO 28，其存储用于未解决的指令的寄存器映射数据，并且指示存储数据的物理寄存器16 可能需要与未解决的投机指示相关联的值。 推测指令可以是预测的分支指令，加载/存储指令，条件指令或其他类型的指令。
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公开(公告)号：US20080114966A1
公开(公告)日：2008-05-15
申请号：US11586007
申请日：2006-10-25
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/384 , G06F9/3863
摘要： A data processing apparatus 2 supports out-of-order processing register renaming using a renaming stage 8. A set of physical registers 16 is mapped to architectural registers. Available-register identifying logic 26 is used to identify which physical registers 16 are available for use by the renaming stage 8. The available-register identifying logic 26 includes an instruction FIFO 28 storing register mapping data for unresolved instructions and indicating physical registers 16 storing data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.
摘要翻译： 数据处理装置2支持使用重命名级8的无序处理寄存器重命名。一组物理寄存器16映射到架构寄存器。 可用寄存器识别逻辑26用于识别哪些物理寄存器16可用于重命名级8.可用寄存器识别逻辑26包括指令FIFO 28，其存储用于未解决的指令的寄存器映射数据，并且指示存储数据的物理寄存器16 可能需要与未解决的投机指示相关联的值。 推测指令可以是预测的分支指令，加载/存储指令，条件指令或其他类型的指令。
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6.发明申请Restoring a register renaming table within a processor following an exception 审中-公开在异常之后还原处理器中的注册表重命名表公开(公告)号：US20080077782A1
公开(公告)日：2008-03-27
申请号：US11526870
申请日：2006-09-26
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/30145 , G06F9/384 , G06F9/3863
摘要： Control logic for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception is disclosed. The processor is operable to process a stream of instructions from an instruction set, the instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way. The processor comprises a physical set of registers operable to store data values being processed by the processor; and register renaming logic operable to receive a stream of decoded instructions and to map for each decoded instruction within the stream of decoded instructions, registers from an architectural set of registers associated with the instruction set to registers within the physical set of registers in dependence upon renaming values stored in the register renaming table; the control logic comprising a buffer and being operable: to identify exception and non-exception instructions within the decoded instruction stream and to group any non-exception instructions with a closest preceding exception instruction; to store in the buffer, register renaming values relating to any registers whose data values are modified by the group of instructions and which are renamed by the register renaming logic as a bundle of register renaming values associated with the exception instruction.
摘要翻译： 公开了用于存储与缓冲器内的未解决的异常指令相关的值的控制逻辑，以使处理器中的寄存器重命名表能够在异常之后恢复。 处理器可操作以处理来自指令集的指令流，包括异常指令和非异常指令的指令集，异常指令是可以产生异常的指令，非异常指令是以静态可确定的方式执行的指令 。 该处理器包括一个物理的寄存器组，用于存储由处理器处理的数据值; 以及寄存器重命名逻辑，其可操作以接收解码指令流并将解码指令流中的每个经解码的指令映射到根据重命名的与寄存器相关联的寄存器与寄存器相关联的寄存器 存储在寄存器重命名表中的值; 控制逻辑包括缓冲器并且可操作：识别解码的指令流内的异常和非异常指令，并且对具有最近的先前异常指令的任何非异常指令进行分组; 要存储在缓冲器中，注册重命名与其数据值被指令组修改并由寄存器重命名逻辑重命名的任何寄存器的重命名值，作为与异常指令相关联的寄存器重命名值。
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7.发明申请Data processing apparatus and method for converting data values between endian formats 有权用于在端序格式之间转换数据值的数据处理装置和方法公开(公告)号：US20080148029A1
公开(公告)日：2008-06-19
申请号：US11637948
申请日：2006-12-13
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30032 , G06F9/3824
摘要： A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided within the data processing apparatus for receiving a block of data containing at least one data value, and for converting each data value in the block from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first predetermined size, in order to produce re-ordered data. Further, second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first predetermined size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format. The swizzle circuitry is responsive to an indication that the at least one data value is of the first predetermined size to output the re-ordered data produced by the first swizzle circuitry, whereas otherwise the swizzle circuitry outputs the data produced by the second swizzle circuitry. This can reduce the complexity of swizzle circuitry provided on a critical path, by optimising the swizzle circuitry to handle endian conversion for data values of the first predetermined size, at the expense of data values that are of other sizes requiring more time for the endian conversion operation to be completed.
摘要翻译： 提供了一种数据处理装置和方法，用于将数据值从第一端格式转换成第二端格式。 在数据处理装置内设置有旋转电路，用于接收包含至少一个数据值的数据块，并将该块中的每个数据值从第一端格式转换为第二端格式。 所述交换电路包括用于对所述数据块执行重新排序操作的第一交换电路，其假设其中包含的所述至少一个数据值具有第一预定大小，以便产生重新排序的数据。 此外，提供了第二旋转电路，其响应于至少一个数据值具有不同于第一预定大小的大小的指示，以对已重新排序的数据执行额外的重新排序操作，其中考虑到 所述至少一个数据值以将每个数据值转换为第二端格式。 交换电路响应于至少一个数据值具有第一预定大小的指示，以输出由第一开关电路产生的重新排序的数据，而否则该转换电路输出由第二开关电路产生的数据。 这可以降低在关键路径上提供的交换电路的复杂性，通过优化旋转电路以处理第一预定大小的数据值的端序转换，代价是需要更多时间用于端序转换的其他大小的数据值 操作完成。
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公开(公告)号：US07590826B2
公开(公告)日：2009-09-15
申请号：US11593151
申请日：2006-11-06
申请人： Florent Begon , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugene Lataille , Frederic Claude Marie Piry
发明人： Florent Begon , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugene Lataille , Frederic Claude Marie Piry
IPC分类号： G06F15/76
CPC分类号： G06F9/3842 , G06F9/384 , G06F9/3863 , G06F11/1008
摘要： A data processing system 2 utilizes a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanism 10, 26 includes a renaming recovery unit 26 which enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unit 26 is used to recover the state of the system 2 in a precise way to that preceding the failing load instruction.
摘要翻译： 数据处理系统2利用寄存器重命名机构10,26将架构寄存器说明符重命名为物理寄存器说明符，以便于无序处理。 寄存器重命名机构10,26包括重命名恢复单元26，其使得能够通过将寄存器映射恢复到在那些不正确的指令之前的状态，使得恢复到不正确执行的推测性指令，使物理寄存器恢复为包含当时当前的数据值 在该错误指令之前。 在加载指令的情况下，这些被视为推测性的，但是响应于加载指令返回并存储在物理寄存器中的数据值在返回时被解除使用，并且在确定结果可用于是否 或者不是该数据值已损坏。 腐败检查采取ECC检查，奇偶校验等形式，并且当产生延迟错误信号时，这指示数据值是否已被正确释放以供使用。 如果检测到损坏，则重命名恢复单元26用于以精确的方式将系统2的状态恢复到故障加载指令之前的状态。
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公开(公告)号：US20080109614A1
公开(公告)日：2008-05-08
申请号：US11593151
申请日：2006-11-06
申请人： Florent Begon , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugene Lataille , Frederic Claude Marie Piry
发明人： Florent Begon , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugene Lataille , Frederic Claude Marie Piry
CPC分类号： G06F9/3842 , G06F9/384 , G06F9/3863 , G06F11/1008
摘要： A data processing system 2 utilises a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanism 10, 26 includes a renaming recovery unit 26 which enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unit 26 is used to recover the state of the system 2 in a precise way to that preceding the failing load instruction.
摘要翻译： 数据处理系统2利用寄存器重命名机构10,26将架构寄存器说明符重命名为物理寄存器说明符，以便于无序处理。 寄存器重命名机构10,26包括重命名恢复单元26，其使得能够通过将寄存器映射恢复到在那些不正确的指令之前的状态，使得恢复到不正确执行的推测性指令，使物理寄存器恢复为包含当时当前的数据值 在该错误指令之前。 在加载指令的情况下，这些被视为推测性的，但是响应于加载指令返回并存储在物理寄存器中的数据值在返回时被解除使用，并且在确定结果可用于是否 或者不是该数据值已损坏。 腐败检查采取ECC检查，奇偶校验等形式，并且当产生延迟错误信号时，这指示数据值是否已被正确释放以供使用。 如果检测到损坏，则重命名恢复单元26用于以精确的方式将系统2的状态恢复到故障加载指令之前的状态。
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公开(公告)号：US08352794B2
公开(公告)日：2013-01-08
申请号：US12591430
申请日：2009-11-19
IPC分类号： G06F11/00
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value.
摘要翻译： 公开了时钟信号控制电路以及用于在模式和计算机程序产品之间切换时钟的方法。 时钟信号控制电路用于从时钟信号发生器接收时钟信号，并将所述时钟信号输出到由所述时钟信号定时的同步电路。 它包括：用于接收指示所述同步电路的模式切换信号的输入是在模式之间切换，所述包括指示所述同步电路的时钟门控请求信号的模式切换信号是进入休眠模式，在该模式期间所述电路不被计时，并且唤醒 指示所述同步电路的上电请求信号将进入所述电路被计时的操作模式; 并且响应于所述时钟选通请求信号来选通所述时钟信号，使得没有时钟信号被输出到所述同步电路并响应于所述唤醒请求信号将所述时钟信号输出到所述同步电路。 时钟信号控制电路还包括：用于存储延迟值的数据存储器; 以及延迟电路，用于响应于所述模式切换信号中的至少一个来延迟所述时钟信号在模式之间的切换，所述延迟电路将所述切换延迟一个取决于所述存储的延迟值的量。
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