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公开(公告)号：US5006815A
公开(公告)日：1991-04-09
申请号：US418414
申请日：1989-10-06
CPC分类号： H03F1/3211 , H03G1/04
摘要： A linear-gain amplifier arrangement comprises a current amplifying cell consisting of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to voltage-current converter (V/I) made up of field-effect transistors. The V/I converter supplies difference currents (I.sub.in1 ; I.sub.in2) which are square-law functions of the input voltage (U.sub.in) to be amplified. The difference between these input currents is a linear function of the input voltage. When the transistors are operated in their saturation regions the difference between the output currents (I.sub.out1 ; I.sub.out2) is also a linear function of the input voltage (U.sub.in). By adding a direct voltage (V.sub.c) to the gate-source voltage of the input and output transistors or by adding a direct current (I.sub.c) to the respective input currents (I.sub.in1 ; I.sub.in2) the gain can be varied without a change in bandwidth. When the arrangement is constructed as an integrated semiconductor circuit its gain can be made immune to temperature variations and tolerances in the fabrication process.
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公开(公告)号：US08606210B2
公开(公告)日：2013-12-10
申请号：US13147779
申请日：2010-02-03
IPC分类号： H04B1/26
CPC分类号： H03D7/165 , H03D7/14 , H03D7/1458 , H03D2200/0086
摘要： A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.
摘要翻译： 一种多相谐波抑制混频器，包括彼此相邻的多个级; 其中第一级布置成至少执行频率转换; 并且第二级被布置为执行至少选择性加权和组合; 其中所述多个级中的至少两个级被布置为执行至少组合。 在一个实施例中，第一级（28）包括三个单端增益块（10,12,14），用于执行选择性加权，频率转换和组合; 和在第一级（28）之后的第二级（30），并被布置成执行选择性加权和组合。 第二级（30）可以减少由第一级（28）输出的相位数，并且可以输出（32）复差分下变频信号。 在第一级中，混频器可以直接接口到无LNA的接收机的天线，而不加权。 混合器可以包括在软件定义的无线电中。
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公开(公告)号：US20110298521A1
公开(公告)日：2011-12-08
申请号：US13147779
申请日：2010-02-03
IPC分类号： G06G7/16
CPC分类号： H03D7/165 , H03D7/14 , H03D7/1458 , H03D2200/0086
摘要： A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.
摘要翻译： 一种多相谐波抑制混频器，包括彼此相邻的多个级; 其中第一级布置成至少执行频率转换; 并且第二级被布置为执行至少选择性加权和组合; 其中所述多个级中的至少两个级被布置为执行至少组合。 在一个实施例中，第一级（28）包括三个单端增益块（10,12,14），用于执行选择性加权，频率转换和组合; 和在第一级（28）之后的第二级（30），并被布置成执行选择性加权和组合。 第二级（30）可以减少由第一级（28）输出的相位数，并且可以输出（32）复差分下变频信号。 在第一级中，混频器可以直接接口到无LNA的接收机的天线，而无需加权。 混合器可以包括在软件定义的无线电中。
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4.发明授权Phase-locked loop including sampling phase detector and charge pump with pulse width control 有权锁相环包括采样相位检测器和带脉冲宽度控制的电荷泵公开(公告)号：US07737743B1
公开(公告)日：2010-06-15
申请号：US12044522
申请日：2008-03-07
申请人： Xiang Gao , Eric A. M. Klumperink , Bram Nauta , Mounir Bohsali , Ali Kiaei , Gerard Socci , Ali Djabbari
发明人： Xiang Gao , Eric A. M. Klumperink , Bram Nauta , Mounir Bohsali , Ali Kiaei , Gerard Socci , Ali Djabbari
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/10
摘要： Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.
摘要翻译： 锁相环（PLL）电路，其中采样相位检测器根据参考信号对输出信号进行采样，并且频率检测器根据参考信号检测输出信号频率。
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