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    System and Method of Processing Hierarchical Very Long Instruction Packets
    2.
    发明申请
    System and Method of Processing Hierarchical Very Long Instruction Packets 有权
    处理分层超长指令包的系统和方法

    公开(公告)号：US20110219212A1

    公开(公告)日：2011-09-08

    申请号：US12716359

    申请日：2010-03-03

    申请人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    发明人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3853 ,  G06F9/30149

    摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

    摘要翻译： 公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。 在特定实施例中，公开了一种处理指令的方法。 该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。 响应于确定该指令包括子分组，该方法还包括执行每个子指令。

    Low latency two-level interrupt controller interface to multi-threaded processor
    3.
    发明授权
    Low latency two-level interrupt controller interface to multi-threaded processor 有权
    低延迟两级中断控制器接口到多线程处理器

    公开(公告)号：US08972642B2

    公开(公告)日：2015-03-03

    申请号：US13252670

    申请日：2011-10-04

    申请人： Suresh K. Venkumahanti ,  Lucian Codrescu ,  Erich James Plondke ,  Xufeng Chen ,  Peixin Zhong

    发明人： Suresh K. Venkumahanti ,  Lucian Codrescu ,  Erich James Plondke ,  Xufeng Chen ,  Peixin Zhong

    IPC分类号： G06F13/24 ,  G06F13/32

    CPC分类号： G06F13/24

    摘要： Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

    摘要翻译： 用于减少多线程处理器中的中断延迟时间的系统和方法。 第一个中断控制器耦合到多线程处理器。 第二中断控制器被配置为将第一中断和第一向量标识符传送到第一中断控制器，其中第一中断控制器被配置为处理第一中断和第一向量标识符，并将经处理的中断发送到多路复用器中的线程 线程处理器 逻辑配置为确定多线程处理器何时准备好接收第二个中断。 专用线路用于向第二中断控制器通知多线程处理器准备好接收第二个中断的指示。

    Methods and Apparatus for Constant Extension in a Processor
    7.
    发明申请
    Methods and Apparatus for Constant Extension in a Processor 审中-公开
    处理器中恒定扩展的方法和装置

    公开(公告)号：US20120284489A1

    公开(公告)日：2012-11-08

    申请号：US13155565

    申请日：2011-06-08

    申请人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    发明人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30192 ,  G06F9/30167

    摘要： Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

    摘要翻译： 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。

    Loop Control System and Method
    8.
    发明申请
    Loop Control System and Method 审中-公开
    回路控制系统和方法

    公开(公告)号：US20090327674A1

    公开(公告)日：2009-12-31

    申请号：US12147893

    申请日：2008-06-27

    申请人： Lucian Codrescu ,  Erich James Plondke ,  Lin Wang ,  Suresh K. Venkumahanti

    发明人： Lucian Codrescu ,  Erich James Plondke ,  Lin Wang ,  Suresh K. Venkumahanti

    IPC分类号： G06F9/30

    CPC分类号： G06F8/4452 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

    摘要： Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

    摘要翻译： 公开了回路控制系统和方法。 在特定实施例中，硬件回路控制逻辑电路包括检测单元以检测程序循环的循环指示符的结束。 硬件回路控制逻辑电路还包括递减单元，用于递减循环计数并递减谓词触发计数器。 硬件循环控制逻辑电路还包括比较单元，用于将谓词触发计数器与参考值进行比较，以确定何时设置谓词值。

    Low Latency Two-Level Interrupt Controller Interface to Multi-Threaded Processor
    9.
    发明申请
    Low Latency Two-Level Interrupt Controller Interface to Multi-Threaded Processor 有权
    低延迟两级中断控制器接口到多线程处理器

    公开(公告)号：US20130086290A1

    公开(公告)日：2013-04-04

    申请号：US13252670

    申请日：2011-10-04

    申请人： Suresh K. Venkumahanti ,  Lucian Codrescu ,  Erich James Plondke ,  Xufeng Chen ,  Peixin Zhong

    发明人： Suresh K. Venkumahanti ,  Lucian Codrescu ,  Erich James Plondke ,  Xufeng Chen ,  Peixin Zhong

    IPC分类号： G06F13/26

    CPC分类号： G06F13/24

    摘要： Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

    摘要翻译： 用于减少多线程处理器中的中断延迟时间的系统和方法。 第一个中断控制器耦合到多线程处理器。 第二中断控制器被配置为将第一中断和第一向量标识符传送到第一中断控制器，其中第一中断控制器被配置为处理第一中断和第一向量标识符，并将经处理的中断发送到多路复用器中的线程 线程处理器 逻辑配置为确定多线程处理器何时准备好接收第二个中断。 专用线路用于向第二中断控制器通知多线程处理器准备好接收第二个中断的指示。