公开(公告)号：US20110087858A1

公开(公告)日：2011-04-14

申请号：US12588263

申请日：2009-10-08

申请人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

发明人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1018 ,  G06F12/1027 ,  G06F12/122

摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

摘要翻译： 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US20100313060A1

公开(公告)日：2010-12-09

申请号：US12656156

申请日：2010-01-19

申请人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

发明人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F15/76 ,  G06F9/06 ,  G06F1/04

CPC分类号： G06F9/30141 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3826 ,  G06F9/3836

摘要： A data processing apparatus and method are provided for performing a predetermined rearrangement operation. The data processing apparatus comprises a vector register bank having a plurality of vector registers, with each vector register comprising a plurality of storage cells such that the plurality of vector registers provide a matrix of storage cells. Each storage cell is arranged to store a data element. A vector processing unit is provided for executing a sequence of vector instructions in order to apply operations to the data elements held in the vector register bank. Responsive to a vector matrix rearrangement instruction specifying a predetermined rearrangement operation to be performed on the data elements in the matrix of storage cells, the vector processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation. When the rearrangement enable signal is set, the write interface then performs a write operation to the storage cells of the matrix using the data elements received at the second input. This enables the predetermined rearrangement operation to be performed at high speed and with significantly less complexity than in prior art systems.

摘要翻译： 提供了一种用于执行预定重排动作的数据处理装置和方法。 数据处理装置包括具有多个向量寄存器的向量寄存器组，每个向量寄存器包括多个存储单元，使得多个向量寄存器提供存储单元矩阵。 每个存储单元被布置成存储数据元素。 向量处理单元被提供用于执行向量指令序列，以便将操作应用于保持在向量寄存器组中的数据元素。 响应于指定对存储单元矩阵中的数据元素执行的预定重排操作的向量矩阵重排指令，向量处理单元被布置为向向量寄存器组发出置位重排使能信号。 修改向量寄存器组的写接口，不仅提供用于在正常执行期间接收由向量处理单元生成的数据元素的第一输入，还具有经由数据重排路径耦合到存储单元矩阵的第二输入 通过其将当前存储在存储单元的矩阵中的数据元素以重新排列的形式提供给写入接口，表示通过执行预定重新排列操作将获得的数据元素的布置。 当重新布置使能信号被设置时，写入接口然后使用在第二输入端接收到的数据元素对矩阵的存储单元进行写入操作。 这使得能够以比现有技术的系统更高的速度和更小的复杂度执行预定的重新排列操作。

公开(公告)号：US20100312988A1

公开(公告)日：2010-12-09

申请号：US12656152

申请日：2010-01-19

申请人： Andreas BJÖRKLUND ,  Erik Persson ,  Ola Hugosson

发明人： Andreas BJÖRKLUND ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F15/00

CPC分类号： G06F9/30072 ,  G06F9/30036 ,  G06F9/30069 ,  G06F9/3887

摘要： A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations.

摘要翻译： 一种用于处理向量指令的数据处理装置和方法。 数据处理装置具有寄存器数据存储器，其具有多个用于存储数据元素的寄存器。 然后，矢量处理单元用于执行矢量指令序列，其中矢量处理单元具有多个并行处理通道，并且能够访问寄存器数据存储器，以便从数据元素读取数据元素， 在执行向量指令序列期间的寄存器数据存储。 跳过指示存储保持每个并行处理通道的跳过指示符。 向量处理单元响应于向量跳过指令执行更新操作，以在跳过指示存储内设置用于所确定的一个或多个车道的跳过指示符。 向量处理单元响应于矢量操作指令，并行地对输入到多个并行处理通道的数据元素执行操作，但是从执行操作排除任何相关联的跳过指示符被设置的通道。 这允许在并行处理的每个通道内有条件地执行由向量指令指定的操作，而不对指定这些操作的向量指令进行任何修改。

公开(公告)号：US08924686B2

公开(公告)日：2014-12-30

申请号：US12588263

申请日：2009-10-08

申请人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

发明人： Erik Persson ,  Ola Hugosson ,  Andreas Björklund

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/10

CPC分类号： G06F12/1018 ,  G06F12/1027 ,  G06F12/122

摘要： A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

摘要翻译： 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US08661225B2

公开(公告)日：2014-02-25

申请号：US12656152

申请日：2010-01-19

申请人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

发明人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F15/00

CPC分类号： G06F9/30072 ,  G06F9/30036 ,  G06F9/30069 ,  G06F9/3887

摘要： A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations.

摘要翻译： 一种用于处理向量指令的数据处理装置和方法。 数据处理装置具有寄存器数据存储器，其具有多个用于存储数据元素的寄存器。 然后，矢量处理单元用于执行矢量指令序列，其中矢量处理单元具有多个并行处理通道，并且能够访问寄存器数据存储器，以便从数据元素读取数据元素， 在执行向量指令序列期间的寄存器数据存储。 跳过指示存储保持每个并行处理通道的跳过指示符。 向量处理单元响应于向量跳过指令执行更新操作，以在跳过指示存储内设置用于所确定的一个或多个车道的跳过指示符。 向量处理单元响应于矢量操作指令，并行地对输入到多个并行处理通道的数据元素执行操作，但是从执行操作排除任何相关联的跳过指示符被设置的通道。 这允许在并行处理的每个通道内有条件地执行由向量指令指定的操作，而不对指定这些操作的向量指令进行任何修改。

公开(公告)号：US08375196B2

公开(公告)日：2013-02-12

申请号：US12656156

申请日：2010-01-19

申请人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

发明人： Andreas Björklund ,  Erik Persson ,  Ola Hugosson

IPC分类号： G06F17/16

CPC分类号： G06F9/30141 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3826 ,  G06F9/3836

摘要： A data processing apparatus includes a vector register bank having a plurality of vector registers, each register including a plurality of storage cells, each cell storing a data element. A vector processing unit is provided for executing a sequence of vector instructions. The processing unit is arranged to issue a set rearrangement enable signal to the vector register bank. The write interface of the vector register bank is modified to provide not only a first input for receiving the data elements generated by the vector processing unit during normal execution, but also has a second input coupled via a data rearrangement path to the matrix of storage cells via which the data elements currently stored in the matrix of storage cells are provided to the write interface in a rearranged form representing the arrangement of data elements that would be obtained by performance of the predetermined rearrangement operation.

摘要翻译： 数据处理装置包括具有多个向量寄存器的向量寄存器组，每个寄存器包括多个存储单元，每个单元存储数据元素。 提供了用于执行向量指令序列的向量处理单元。 处理单元被布置成向向量寄存器组发出一个置位重排使能信号。 修改向量寄存器组的写接口，不仅提供用于在正常执行期间接收由向量处理单元生成的数据元素的第一输入，还具有经由数据重排路径耦合到存储单元矩阵的第二输入 通过其将当前存储在存储单元的矩阵中的数据元素以重新排列的形式提供给写入接口，表示通过执行预定重新排列操作将获得的数据元素的布置。

公开(公告)号：US20120051437A1

公开(公告)日：2012-03-01

申请号：US12923083

申请日：2010-08-31

申请人： Andreas Björklund ,  Ola Hugosson

发明人： Andreas Björklund ,  Ola Hugosson

IPC分类号： H04N7/12

CPC分类号： H04N19/423 ,  H04N19/44

摘要： A video processing apparatus, method and computer program are disclosed. The video processing apparatus comprises: first stage video processing circuitry for receiving a bitstream of compressed encoded video data representing a plurality of frames of video data and configured to perform one or more processing operations on the input compressed video data; analysing circuitry configured to analyse the processed bitstream and to determine for at least one of the plurality of frames at least one portion of the at least one frame that is not required in the decoding of other frames and to generate at least one indicator indicating the at least one portion. The frame reconstruction processing circuitry is configured to perform frame reconstruction on the compressed encoded video data and to receive the at least one indicator and to generate at least one partial reference frame for use in decoding other frames from the bitstream and the at least one indicator, the frame reconstruction processing circuitry being configured to determine from the at least one indicator the at least one portion that is not required for decoding other frames and to generate the partial reference frame as a frame that does not include the at least one portion and to output the partial reference frame for use in decoding the other frames.

摘要翻译： 公开了一种视频处理装置，方法和计算机程序。 视频处理装置包括：第一级视频处理电路，用于接收表示多个视频数据帧的压缩编码视频数据的比特流，并配置为对输入的压缩视频数据执行一个或多个处理操作; 分析电路，被配置为分析所处理的比特流，并且为所述多个帧中的至少一个帧确定所述至少一个帧中的至少一个部分，所述至少一个部分在其他帧的解码中不是必需的，并且生成至少一个指示 至少一部分。 帧重建处理电路被配置为对压缩的编码视频数据执行帧重构并且接收至少一个指示符并且生成用于从比特流和至少一个指示符解码其他帧的至少一个部分参考帧， 所述帧重建处理电路被配置为从所述至少一个指示符确定所述至少一个部分，所述至少一个部分不是解码其他帧所必需的，并且将所述部分参考帧生成为不包括所述至少一个部分的帧，并且输出 用于解码其他帧的部分参考帧。

公开(公告)号：US08594177B2

公开(公告)日：2013-11-26

申请号：US12923083

申请日：2010-08-31

申请人： Andreas Björklund ,  Ola Hugosson

发明人： Andreas Björklund ,  Ola Hugosson

IPC分类号： H04N7/26 ,  H04N7/50

CPC分类号： H04N19/423 ,  H04N19/44

摘要： A video processing apparatus, method and computer program are disclosed. The video processing apparatus comprises: first stage video processing circuitry for receiving a bitstream of compressed encoded video data representing a plurality of frames of video data and configured to perform one or more processing operations on the input compressed video data; analyzing circuitry configured to analyze the processed bitstream and to determine for at least one of the plurality of frames at least one portion of the at least one frame that is not required in the decoding of other frames and to generate at least one indicator indicating the at least one portion. The frame reconstruction processing circuitry is configured to perform frame reconstruction on the compressed encoded video data and to receive the at least one indicator and to generate at least one partial reference frame for use in decoding other frames from the bitstream and the at least one indicator, the frame reconstruction processing circuitry being configured to determine from the at least one indicator the at least one portion that is not required for decoding other frames and to generate the partial reference frame as a frame that does not include the at least one portion and to output the partial reference frame for use in decoding the other frames.

摘要翻译： 公开了一种视频处理装置，方法和计算机程序。 视频处理装置包括：第一级视频处理电路，用于接收表示多个视频数据帧的压缩编码视频数据的比特流，并配置为对输入的压缩视频数据执行一个或多个处理操作; 分析电路，被配置为分析所处理的比特流，并且为所述多个帧中的至少一个帧确定所述至少一个帧中的至少一个部分，所述至少一个部分在其他帧的解码中不是必需的，并且生成至少一个指示 至少一部分。 帧重建处理电路被配置为对压缩的编码视频数据执行帧重构并且接收至少一个指示符并且生成用于从比特流和至少一个指示符解码其他帧的至少一个部分参考帧， 所述帧重建处理电路被配置为从所述至少一个指示符确定所述至少一个部分，所述至少一个部分不是解码其他帧所必需的，并且将所述部分参考帧生成为不包括所述至少一个部分的帧，并且输出 用于解码其他帧的部分参考帧。

公开(公告)号：US09591319B2

公开(公告)日：2017-03-07

申请号：US12926909

申请日：2010-12-16

申请人： Ola Hugosson ,  Erik Persson

发明人： Ola Hugosson ,  Erik Persson

IPC分类号： H04B1/66 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/436 ,  H04N19/51 ,  H04N19/61 ,  H04N19/423

CPC分类号： H04N19/436 ,  H04N19/423 ,  H04N19/51 ,  H04N19/61

摘要： A video encoding apparatus for encoding a video stream comprises a reference frame cache for reference frame video data retrieved from a reference frame storage unit in external memory, which is derived from an individual frame of the video stream. First and second source frame storage units store first and second blocks of unencoded video data taken from first and second source frames of the video stream, respectively. First and second video encoders perform first and second encoding operations to encode the first and second blocks of unencoded video data with reference to the reference frame video data cached in the reference frame cache, respectively. The first video encoder and the second video encoder perform the first encoding operation and the second encoding operation in parallel with one another.

摘要翻译： 一种用于编码视频流的视频编码装置包括从外部存储器中的参考帧存储单元检索的参考帧视频数据，该参考帧高速缓存从视频流的单独帧导出。 第一和第二源帧存储单元分别存储从视频流的第一和第二源帧中取出的未编码视频数据的第一和第二块。 第一和第二视频编码器执行第一和第二编码操作，分别参考缓存在参考帧高速缓冲存储器中的参考帧视频数据对第一和第二未编码视频数据块进行编码。 第一视频编码器和第二视频编码器彼此并行执行第一编码操作和第二编码操作。

公开(公告)号：US20110191539A1

公开(公告)日：2011-08-04

申请号：US12656570

申请日：2010-02-03

申请人： Ola Hugosson ,  Erik Persson ,  Pontus Borg

发明人： Ola Hugosson ,  Erik Persson ,  Pontus Borg

IPC分类号： G06F15/76 ,  G06F9/06 ,  G06F12/10 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/06 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F15/76

摘要： A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data.

摘要翻译： 提供了一种数据处理装置，其被配置为代表主数据处理装置执行数据处理操作，包括被配置为执行数据处理操作的协处理器核心和被配置为使协处理器核心复位的复位控制器。 协处理器内核根据存储在其中的当前配置数据执行其数据处理，当前配置数据与当前处理会话相关联。 复位控制器被配置为从主数据处理设备接收待处理的配置数据，与待处理的处理会话相关联的未决配置数据，以及将未决配置数据存储在配置数据队列中。 配置复位控制器，当协处理器内核复位时，将待配置数据从配置数据队列传输到存储在协处理器内核中，替换当前配置数据。