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公开(公告)号：US07941610B2
公开(公告)日：2011-05-10
申请号：US11413158
申请日：2006-04-27
申请人： Erin A. Handgen , Patrick Knebel
发明人： Erin A. Handgen , Patrick Knebel
CPC分类号： G06F12/0817 , G06F2212/2542 , Y02D10/13
摘要： Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache including an entry for each of a plurality of coherency units, each coherency unit included in a memory block representing a contiguous portion of the plurality of memory resources. A controller is operably connected to the interconnect fabric. The controller is configured to control a portion of the plurality of memory resources, and has a comparator configured to identify whether a memory block is local. If the memory block is local, the controller is configured to set a state of the directory to exclusive for a write transaction. If the memory block is not local, the controller is configured to set the state to invalid for a write transaction.
摘要翻译： 在多处理器计算系统中提供了一致性目录更新。 多个存储器资源具有目录，并且可操作地连接到互连结构。 电池可操作地连接到互连织物。 该小区具有包括多个相关性单元中的每一个的条目的高速缓存，每个相关性单元包括在表示多个存储器资源的连续部分的存储器块中。 控制器可操作地连接到互连结构。 控制器被配置为控制多个存储器资源的一部分，并且具有被配置为识别存储器块是否是本地的比较器。 如果内存块是本地的，则控制器被配置为将目录的状态设置为独占的写事务。 如果内存块不是本地的，则控制器被配置为将写入事务的状态设置为无效。
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公开(公告)号：US08505020B2
公开(公告)日：2013-08-06
申请号：US12870835
申请日：2010-08-29
IPC分类号： G06F9/46 , G06F15/173 , G06F1/00 , G06F11/00
CPC分类号： G06F9/5088
摘要： An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.
摘要翻译： 检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。 工作负载的处理被分配给处理单元的第二处理器集合，使得在源处理器集上执行一些工作负载过程，并且在第二处理器单元集合上执行一些工作负载过程。 然后，一些工作负载过程被分配给第二处理器集，使得在源处理器集上不执行工作负载过程，并且至少一些所述进程在第二进程集上执行。 第二处理器集合可以是目标处理器集合或中间处理器集合，工作负载从该集中迁移到目标处理器集合。
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公开(公告)号：US20080104329A1
公开(公告)日：2008-05-01
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。
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4.发明授权Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions 失效用于在用微指令进行仿真时，在生成和消耗宏指令之间有效地生成，存储和消耗算术标记的方法和装置公开(公告)号：US06807625B1
公开(公告)日：2004-10-19
申请号：US09507032
申请日：2000-02-18
申请人： Patrick Knebel , Mark Gibson , Rohit Bhatia , Kevin David Safford
发明人： Patrick Knebel , Mark Gibson , Rohit Bhatia , Kevin David Safford
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30094 , G06F9/3842
摘要： An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.
摘要翻译： 一种用于在计算机系统中有效地产生算术标志的装置和方法。 该系统包括用于存储由算术逻辑单元计算的部分计算的标志的eflags寄存器。 存储的部分标志在一个周期内计算。 存储的标志在第二个周期中由两个消耗指令PRODF或TBIT中的一个解码。
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公开(公告)号：US08683139B2
公开(公告)日：2014-03-25
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。
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6.发明授权Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit 有权用于验证中央处理器单元的行为模型的细粒度正确性的方法和装置公开(公告)号：US06625759B1
公开(公告)日：2003-09-23
申请号：US09502366
申请日：2000-02-18
申请人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
发明人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
IPC分类号： H02H305
CPC分类号： G06F11/261
摘要： A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.
摘要翻译： 一种方法和装置检查微码机中央处理器单元（CPU）行为模型的细粒度正确性。 宏指令被分解为微指令，并且每个微指令都被顺序执行。 微指令序列由模拟的微指令测序仪确定，使用动态执行信息，包括在微指令序列中执行先前微指令的信息。 在每个微指令的执行结束时，将参考状态与行为模型的相应状态进行比较，并且注意到任何差异。 在微指令序列中执行所有微指令之后，将参考状态与行为模型的相应状态进行比较，并记录任何差异。
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7.发明授权Circuitry for providing external access to signals that are internal to an integrated circuit chip package 失效用于提供对集成电路芯片封装内部信号的外部访问的电路
公开(公告)号：US6003107A
公开(公告)日：1999-12-14
申请号：US707936
申请日：1996-09-10
CPC分类号： G06F7/02
摘要： Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.
摘要翻译： 用于提供对集成电路芯片封装内部信号的外部访问的电路。 多个N：1复用器物理地分布在整个集成电路管芯中。 每个复用器具有其N个输入耦合到集成电路内的附近的一组N个节点，并且每个多路复用器耦合到可选择信息的源，用于从用于外部访问的N个节点的集合中选择一个节点。 每个多路复用器的输出耦合到外部可访问的芯片焊盘。 集成电路是微处理器，选择信息的源可以包括存储元件。 如果是这样，则提供附加电路用于使用一个或多个微处理器指令将数据从微处理器的寄存器写入存储元件。 每个复用器可以耦合到不同的选择信息源，或者所有复用器可以耦合到相同的选择信息。 此外，可以提供固定的一组互连轨迹以将固定的一组节点耦合到另外一组外部可访问的芯片焊盘。 还可以提供一个或多个M：1多路复用器，其M个输入端耦合到N：1多路复用器的M个不同输出。 M：1多路复用器中的每一个可以耦合到第二选择信息源。 优选地，M：1多路复用器的输出将耦合到用于促进集成电路的调试和性能监视的电路。
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8.发明授权System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions 失效用于操作数旁路的系统允许一个半周期的缓存存储器访问时间用于顺序加载和分支指令
公开(公告)号：US5526500A
公开(公告)日：1996-06-11
申请号：US387960
申请日：1995-02-10
申请人： Darius F. Tanksalvala , Eric R. DeLano , Patrick Knebel , Thomas R. Hotchkiss , R. Craig Simpson
发明人： Darius F. Tanksalvala , Eric R. DeLano , Patrick Knebel , Thomas R. Hotchkiss , R. Craig Simpson
CPC分类号： G06F12/0888 , G06F12/0855 , G06F9/3824 , G06F9/3842
摘要： Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.
摘要翻译： 管道结构被布置为允许数据和指令高速缓存的1.5个周期访问时间，而不施加比具有1个周期访问时间的数据和指令高速缓存所施加的额外的指令阶延迟。 产生半周期脉冲以允许在0.5个周期内执行各种指令。 生成旁路信号以允许来自当前加载指令的数据可用于第二后续指令，即使数据高速缓存的访问时间为1.5个周期。 另外，即使指令高速缓存访问时间为1.5个周期，分支地址也可用于第三个后续指令。 本发明示出了针对高速缓冲存储器的每个周期和1.5周期访问时间的指令步骤的启动。 本发明还可以通过每2个周期实现一个指令并为高速缓冲存储器提供3个周期的访问时间来实现。
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9.发明授权Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition 失效在测试条件故障时有条件地冲洗管道的装置和方法公开(公告)号：US06745322B1
公开(公告)日：2004-06-01
申请号：US09507505
申请日：2000-02-18
IPC分类号： G06F944
CPC分类号： G06F9/30174 , G06F9/322 , G06F9/3806 , G06F9/3861
摘要： A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e.g., to flush stale instructions.
摘要翻译： 描述了使用简单的测试和刷新机制来使用另一个ISA的指令来实现一个指令集架构（ISA）的分支指令的方法和装置。 在实现分支指令的微指令的解码和排序期间，确定并存储在错误的目标或分支条件的情况下表示补救分支目标的修正地址。 设置测试条件以确定预测或分支条件是否正确。 当测试条件失败时，立即刷新指令执行流水线，以避免在分支指令之后执行流水线中剩余的任何指令。 流水线的冲洗通知指令获取控制机制，将指令流重定向到与固定地址对应的指令。 根据本发明的方法和装置进一步允许在发生分支指令中涉及的条件以外的条件时冲洗管道，例如冲洗陈旧的指令。
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10.发明授权Method and apparatus for emulating an instruction set extension in a digital computer system 有权用于在数字计算机系统中仿真指令集扩展的方法和装置公开(公告)号：US06681322B1
公开(公告)日：2004-01-20
申请号：US09449846
申请日：1999-11-26
IPC分类号： G06F900
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30101 , G06F9/30112 , G06F9/30174 , G06F9/3865 , G06F9/45504
摘要： Methods for emulating an instruction set extension, comprising providing data to be operated upon, executing a first instruction with respect to a first portion of the data without committing the results of the first executed instruction, if no unmasked exceptions occur with respect to the first portion of the data, executing a second instruction with respect to a second portion of the data, and if no unmasked exceptions occur with respect to the second portion of the data, committing the results of the second executed instruction and again executing the first instruction with respect to the first portion of the data. If the first instruction is executed again, its results are committed. A handler is invoked if an unmasked exception occurs.
摘要翻译： 用于模拟指令集扩展的方法，包括提供要操作的数据，相对于所述数据的第一部分执行第一指令而不提交所述第一执行指令的结果，如果没有相对于所述第一部分发生未被掩蔽的异常 相对于数据的第二部分执行第二指令，并且如果相对于数据的第二部分没有发生未被屏蔽的异常，则提交第二执行指令的结果并再次执行第一指令 到数据的第一部分。 如果再次执行第一条指令，则其结果将被提交。 如果发生未屏蔽的异常，则调用处理程序。
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