公开(公告)号：US07827325B2

公开(公告)日：2010-11-02

申请号：US11931689

申请日：2007-10-31

申请人： Etai Adar ,  Ilya Granovsky ,  Zorik Machulsky ,  Paul J. Mattos

发明人： Etai Adar ,  Ilya Granovsky ,  Zorik Machulsky ,  Paul J. Mattos

IPC分类号： G06F13/38

CPC分类号： G06F13/387

摘要： A mechanism for speculative packet transmission including a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if the number of available flow control (FC) credits is insufficient for completing the transmission. The sending device initiates a speculative transmission of packets to the receiving device even though the packet for transmission requires a number of FC credits greater than the available FC credits. If the additional FC credits required to complete the packet transmission become available to the sending device before the transmission is completed, the packets are then fully transmitted by the sending device. Otherwise, if the additional FC credits required do not become available prior to completion of the transmission, then the sending device aborts the transmission without utilization of the FC credits. The sending device may initiate speculative packet transmission only if a particular minimal amount of FC credits is available.

摘要翻译： 一种用于推测分组传输的机制，包括基于信用的流控制互连设备，用于如果可用流控制（FC）信用的数量不足以完成传输，则启动事务层分组的推测传输。 发送设备发起分组到接收设备的推测传输，即使用于传输的分组需要大于可用FC信用的多个FC信用。 如果完成分组传输所需的附加FC信用在发送完成之前对发送设备可用，则发送设备将完全发送分组。 否则，如果在完成传输之前所​​需的附加FC信用不可用，则发送设备在不使用FC信用的情况下中止传输。 只有当特定的最小量的FC信用可用时，发送设备才能启动推测性分组传输。

公开(公告)号：US09086965B2

公开(公告)日：2015-07-21

申请号：US13326457

申请日：2011-12-15

申请人： Etai Adar ,  Ilya Granovsky

发明人： Etai Adar ,  Ilya Granovsky

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0793

摘要： An apparatus and method of PCIe error handling and recovery actions taken in the event of an error. An error reporting extension defines a set of commonly used actions that are taken by a device in response to the detection of an error. This minimizes the side effects of continued device operation following the occurrence of an error. The device's error handling capabilities are advertised and the system software specifies the desired device action to take upon occurrence of a particular error. The particular error handling action is defined uniquely for each PCIe function and error type, such that different errors trigger a different type of action, thereby affecting only specific device functions or the entire device, depending on the configuration. Error handling actions and control fields are placed in the extension portion of the PCI Express Advanced Error Reporting configuration space.

摘要翻译： 发生错误时采取的PCIe错误处理和恢复操作的装置和方法。 错误报告扩展定义了响应于错误检测而由设备采取的一组常用动作。 这最大限度地减少了发生错误后持续的设备操作的副作用。 通告设备的错误处理能力，并且系统软件指定出现特定错误时需要的设备操作。 针对每个PCIe功能和错误类型唯一地定义了特定的错误处理动作，因此不同的错误触发了不同类型的动作，从而仅根据配置影响特定的设备功能或整个设备。 错误处理操作和控制字段被放置在PCI Express高级错误报告配置空间的扩展部分。

公开(公告)号：US08024597B2

公开(公告)日：2011-09-20

申请号：US12034896

申请日：2008-02-21

申请人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

发明人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

IPC分类号： G06F1/04

CPC分类号： G06F1/12 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31937

摘要： The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.

摘要翻译： 本发明实现了一种使得零延迟验证工具能够检测包括两个不同时钟域的设备中的时钟域交叉违反的机制，其中快速时钟速率是通过插入未定义的（即，无效的 ）时钟周期内的慢时钟域信号值。 未定义的值包含在逻辑锥中并模拟路径的时序不确定度。 通过捕获锁存器传播未定义的值表示不正确的时钟域穿越处理。

公开(公告)号：US07734854B2

公开(公告)日：2010-06-08

申请号：US11969475

申请日：2008-01-04

申请人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

发明人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

IPC分类号： G06F13/36

CPC分类号： G06F13/362

摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.

摘要翻译： 一些实施例包括例如处理事务的设备，系统和方法。 在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。 由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

公开(公告)号：US09032102B2

公开(公告)日：2015-05-12

申请号：US13411203

申请日：2012-03-02

申请人： Ilya Granovsky ,  Etai Adar

发明人： Ilya Granovsky ,  Etai Adar

IPC分类号： G06F13/36 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F13/36 ,  G06F13/385

摘要： An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

摘要翻译： 一种使用目标功能数据查找表的快速PCIe多功能设备地址解码的设备和方法。 在PCIe请求分组内提供一个或多个解码指令（例如，目标函数），从而消除在端点设备中的解码过程期间对目标函数搜索的需要。 这使得复杂多功能设备中的单解码器单步解码实现成为可能。

公开(公告)号：US20130232279A1

公开(公告)日：2013-09-05

申请号：US13411203

申请日：2012-03-02

申请人： Etai Adar ,  Ilya Granovsky

发明人： Etai Adar ,  Ilya Granovsky

IPC分类号： G06F13/36 ,  G06F3/00

CPC分类号： G06F9/30145 ,  G06F13/36 ,  G06F13/385

摘要： An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.

摘要翻译： 一种使用目标功能数据查找表的快速PCIe多功能设备地址解码的设备和方法。 在PCIe请求分组内提供一个或多个解码指令（例如，目标函数），从而消除在端点设备中的解码过程期间对目标函数搜索的需要。 这使得复杂多功能设备中的单解码器单步解码实现成为可能。

公开(公告)号：US20090217075A1

公开(公告)日：2009-08-27

申请号：US12034896

申请日：2008-02-21

申请人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

发明人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

IPC分类号： G06F1/04

CPC分类号： G06F1/12 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31937

摘要： The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violation in device under test designs comprising two different clock domains where the fast clock is an integer multiple of the slow clock by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainly of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.

摘要翻译： 本发明实现了一种使得零延迟验证工具能够检测包括两个不同时钟域的设备中的时钟域交叉违规的机制，其中快速时钟是慢时钟的整数倍，通过插入未定义的（即，无效的）值 在不应该捕获信号的时钟周期内的慢时钟域信号。 未定义的值包含在逻辑锥中，并且不确定地模拟路径的时序。 通过捕获锁存器传播未定义的值表示不正确的时钟域穿越处理。

公开(公告)号：US20090185487A1

公开(公告)日：2009-07-23

申请号：US12017432

申请日：2008-01-22

申请人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

发明人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

IPC分类号： H04L1/00

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.

摘要翻译： 这里的实施例提供了一种事务级别机制，其确保链路在时间上对于数据流动是正确的操作，使得数据流不会受到与链路恢复到操作状态相关联的延迟的影响。 路径具有能够处于非活动模式或活动模式的链接。 这里的实施例在发送数据传输（包括分组化数据）之前在路径内打开路径上的链路​​来传送“激活传输”，以打开（唤醒）路径内的非活动链路，使得实际数据 转移不会发生任何此类启动或唤醒延迟。

公开(公告)号：US20130159764A1

公开(公告)日：2013-06-20

申请号：US13326457

申请日：2011-12-15

申请人： Etai Adar ,  Ilya Granovsky

发明人： Etai Adar ,  Ilya Granovsky

IPC分类号： G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0793

摘要： An apparatus and method of PCIe error handling and recovery actions taken in the event of an error. An error reporting extension defines a set of commonly used actions that are taken by a device in response to the detection of an error. This minimizes the side effects of continued device operation following the occurrence of an error. The device's error handling capabilities are advertised and the system software specifies the desired device action to take upon occurrence of a particular error. The particular error handling action is defined uniquely for each PCIe function and error type, such that different errors trigger a different type of action, thereby affecting only specific device functions or the entire device, depending on the configuration. Error handling actions and control fields are placed in the extension portion of the PCI Express Advanced Error Reporting configuration space.

摘要翻译： 发生错误时采取的PCIe错误处理和恢复操作的装置和方法。 错误报告扩展定义了响应于错误检测而由设备采取的一组常用动作。 这最大限度地减少了发生错误后持续的设备操作的副作用。 通告设备的错误处理能力，并且系统软件指定出现特定错误时需要的设备操作。 针对每个PCIe功能和错误类型唯一地定义了特定的错误处理动作，因此不同的错误触发了不同类型的动作，从而仅根据配置影响特定的设备功能或整个设备。 错误处理操作和控制字段被放置在PCI Express高级错误报告配置空间的扩展部分。

公开(公告)号：US20090187683A1

公开(公告)日：2009-07-23

申请号：US12017735

申请日：2008-01-22

申请人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

发明人： Etai Adar ,  Michael Bar-Joshua ,  Ilya Granovsky ,  Shaul Yifrach

IPC分类号： G06F3/00

CPC分类号： H04L47/10 ,  H04L47/2416

摘要： A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption.

摘要翻译： 通信装置使用至少一个逻辑通信链路，其包括计算机化的硬件设备内的多条通道。 数据传输监视器连接到逻辑通信链路，并测量逻辑通信链路的实时数据传输带宽。 此外，链路管理单元或链路宽度控制单元（比较器）连接到通道和数据传输监视器，并将实时数据传输带宽连续地与预定的数据传输带宽标准进行比较。 如果实时数据传输带宽低于预定的数据传输带宽标准，则链路管理单元适于通过激活附加通道来执行逻辑通信链路的上配置，最多数目的通道组成逻辑通信链路 。 相反，如果实时数据传输带宽高于预定的数据传输带宽标准，则链路管理单元适于通过停用逻辑通信链路内的通道来执行逻辑通信链路的下配置。 当通道相对于通道被激活时，通道消耗较少的功率，因此下配置降低功耗。