公开(公告)号：US07505020B2

公开(公告)日：2009-03-17

申请号：US10923077

申请日：2004-08-23

申请人： Etsuo Yamamoto ,  Seijirou Gyouten ,  Sachio Tsujino ,  Hoh Riku

发明人： Etsuo Yamamoto ,  Seijirou Gyouten ,  Sachio Tsujino ,  Hoh Riku

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/04 ,  G09G2330/021

摘要： A simultaneous precharge type display device source driver includes supply control circuits each of which is provided on each of source bus lines. Each of the supply control circuits receives (a) a precharge control signal for precharging each of the source bus line and (b) a sampling control signal for writing data, which should be written on pixels, onto the source bus line. The one of two switches turns ON in response to the precharge control signal and the sampling control signal. The other of the switches turns ON in response to the sampling control signal. In the sampling operation, both the switches are turned ON so as to quicken the writing operation. In the precharge operation, the other switch does not operate, so that it is possible to reduce the power consumption.

摘要翻译： 同时预充电型显示装置源驱动器包括各源极总线上的供给控制电路。 每个供电控制电路接收（a）用于对源总线进行预充电的预充电控制信号，以及（b）用于将应写入像素的数据写入源总线的采样控制信号。 两个开关中的一个响应于预充电控制信号和采样控制信号而导通。 响应于采样控制信号，另一个开关变为ON。 在采样操作中，两个开关都接通，以便加快写入操作。 在预充电操作中，另一个开关不工作，从而可以降低功耗。

公开(公告)号：US20050052443A1

公开(公告)日：2005-03-10

申请号：US10923077

申请日：2004-08-23

申请人： Etsuo Yamamoto ,  Seijirou Gyouten ,  Sachio Tsujino ,  Hoh Riku

发明人： Etsuo Yamamoto ,  Seijirou Gyouten ,  Sachio Tsujino ,  Hoh Riku

IPC分类号： G02F1/133 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/02 ,  H01L51/50 ,  H05B33/14

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/04 ,  G09G2330/021

摘要： A simultaneous precharge type display device source driver includes supply control circuits each of which is provided on each of source bus lines. Each of the supply control circuits receives (a) a precharge control signal for precharging each of the source bus line and (b) a sampling control signal for writing data, which should be written on pixels, onto the source bus line. The one of two switches turns ON in response to the precharge control signal and the sampling control signal. The other of the switches turns ON in response to the sampling control signal. In the sampling operation, both the switches are turned ON so as to quicken the writing operation. In the precharge operation, the other switch does not operate, so that it is possible to reduce the power consumption.

摘要翻译： 同时预充电型显示装置源驱动器包括各源极总线上的供给控制电路。 每个供电控制电路接收（a）用于对源总线进行预充电的预充电控制信号，以及（b）用于将应写入像素的数据写入源总线的采样控制信号。 两个开关中的一个响应于预充电控制信号和采样控制信号而导通。 响应于采样控制信号，另一个开关变为ON。 在采样操作中，两个开关都接通，以便加快写入操作。 在预充电操作中，另一个开关不工作，从而可以降低功耗。

公开(公告)号：US08248348B2

公开(公告)日：2012-08-21

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175 ,  H03L5/00 ,  G09G5/00 ,  G09G3/28 ,  G09G3/36

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

公开(公告)号：US07289097B2

公开(公告)日：2007-10-30

申请号：US10702077

申请日：2003-11-06

申请人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

发明人： Seijirou Gyouten ,  Sachio Tsujino ,  Hajime Washio ,  Eiji Matsuda ,  Keiichi Ina ,  Yuhichiroh Murakami ,  Shunsuke Hayashi ,  Mamoru Onda

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0289 ,  G11C19/00 ,  G11C19/28

摘要： The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

摘要翻译： 本发明公开了一种扫描方向控制电路，其包括双向移位寄存器，其中根据切换信号L / R切换移位方向，当切换信号L / R在比驱动电压低的振幅时由电平移位器升压。 扫描方向控制电路包括电平移位器和双向移位寄存器之间的锁存电路，并且控制电路使得锁存电路在构成双向移位寄存器的触发器的移位操作之后响应于输出而完成锁存操作 触发器的信号。 控制电路在锁存定时之前，之后和之后的时段中使电平移位器进入有效状态，并且在剩余时间段内使电平移位器进入非活动状态。 利用这种布置，可以在低功耗的情况下以预定的时序提供开关信号L / R，而不管其外部输入定时。

公开(公告)号：US07733321B2

公开(公告)日：2010-06-08

申请号：US11543219

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

公开(公告)号：US20070242021A1

公开(公告)日：2007-10-18

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

公开(公告)号：US20100259529A1

公开(公告)日：2010-10-14

申请号：US12734394

申请日：2008-09-01

申请人： Shuji Nishi ,  Sachio Tsujino ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

发明人： Shuji Nishi ,  Sachio Tsujino ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

IPC分类号： G09G5/00 ,  G05F3/24

CPC分类号： H02M3/073 ,  H02M2003/077

摘要： An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

摘要翻译： 本发明的一个实施例提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。 当在升压部中的第一电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第三电容器，进一步升高电压，从而导通第一晶体管。 当在升压部中的第二电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第四电容器，进一步升压电压，从而导通第二晶体管。 这种布置消除了用作输出侧开关元件的第一和第二晶体管中的阈值电压下降的问题。

公开(公告)号：US07688302B2

公开(公告)日：2010-03-30

申请号：US11543218

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

公开(公告)号：US20100245327A1

公开(公告)日：2010-09-30

申请号：US12733813

申请日：2008-07-24

申请人： Sachio Tsujino ,  Shuji Nishi ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

发明人： Sachio Tsujino ,  Shuji Nishi ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten

IPC分类号： G09G5/00 ,  G05F3/02

CPC分类号： H02M3/073

摘要： An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between −VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively. In this arrangement, the driver section 11b generates signals each having a voltage alternating between VDD and 3VDD, as the control signals.

摘要翻译： 本发明的目的是提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。 在升压部（11a）中，电容器（C1）和（C2）分别具有与晶体管（Q1，Q3）和（Q2，Q4）相连的各自的第一端子。 每个晶体管的栅极端子提供有在驱动器部分（11b）中产生的控制信号。 驱动器部分（11b）包括与输入端子（Ti3，Ti4）连接的电容器（C3，C4），用于各自提供时钟信号DCK2，DCK2B，每个时钟信号具有在-VDD和VDD之间交替的电压（VDD表示来自外部的输入电源电压 ）作为分别提供给电容器（C1，C2）的第二端子的时钟信号DCK1，DCK1B的电平移位信号。 在这种布置中，驱动器部分11b产生各自具有在VDD和3VDD之间交替的电压的信号作为控制信号。

公开(公告)号：US20070024568A1

公开(公告)日：2007-02-01

申请号：US11543219

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.