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公开(公告)号：US07930655B2
公开(公告)日：2011-04-19
申请号：US12117379
申请日：2008-05-08
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US07395522B2
公开(公告)日：2008-07-01
申请号：US10801310
申请日：2004-03-16
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US07039556B2
公开(公告)日：2006-05-02
申请号：US10867003
申请日：2004-06-14
CPC分类号： G05B19/41875 , G05B2219/37224 , G05B2219/45031 , Y02P90/22
摘要： A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.
摘要翻译： 用于分析制造工艺的系统，例如分析衬底上的器件产量。 输入访问制造信息，其中制造信息包括与衬底位置信息相关联的因变量中的至少一个以及与至少一个制造过程相关联的至少一个独立变量。 基于自变量和因变量中的至少一个，选择衬底信息的期望部分。 基于制造信息的期望部分产生衬底轮廓。
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公开(公告)号：US07137098B2
公开(公告)日：2006-11-14
申请号：US10927802
申请日：2004-08-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H01L21/70
摘要： A method for determining component patterns of a raw substrate map. A subset of substrate patterns is selected from a set of substrate patterns, and combined into a composite substrate map. The substrate patterns are weighted. The composite substrate map is compared to the raw substrate map, and a degree of correlation between the composite substrate map and the raw substrate map is determined. The steps are iteratively repeated until the degree of correlation is at least a desired degree, and the weighted subset of substrate patterns is output as the component patterns of the raw substrate map.
摘要翻译： 一种用于确定原始底物图的组分图案的方法。 衬底图案的子集从一组衬底图案中选择，并组合成复合衬底图。 衬底图案被加权。 将复合衬底图与原始衬底图进行比较，并确定复合衬底图与原始衬底图之间的相关程度。 迭代重复这些步骤，直到相关度至少达到期望的程度，并且将基底图案的加权子集输出为原始底物图的组分图案。
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公开(公告)号：US20080216048A1
公开(公告)日：2008-09-04
申请号：US12117379
申请日：2008-05-08
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
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公开(公告)号：US07062415B2
公开(公告)日：2006-06-13
申请号：US10928292
申请日：2004-08-27
IPC分类号： G06F17/00
CPC分类号： G05B17/02 , G06T7/0004 , G06T2207/20076 , G06T2207/30148
摘要： A method for determining outlier data points in. A subset of dataset patterns is selected from a set of mathematical dataset patterns, and the subset of dataset patterns is combined into a composite dataset. The composite dataset is compared to the dataset, and a degree of correlation between the composite dataset and the dataset is determined. Data points within the composite dataset are selectively weighted to improve the degree of correlation, and the steps described above are selectively iteratively repeated until the degree of correlation is at least a desired value. Residuals for the data points within the composite dataset are selectively determined. At least one of the weighted data points within the composite dataset that are weighted within a first specified range, and data points within the composite dataset that have a residual within a second specified range, are selectively output as outlier data points.
摘要翻译： 一种用于确定异常数据点的方法。从一组数学数据集模式中选择数据集模式的子集，并将数据集模式的子集组合成一个复合数据集。 将复合数据集与数据集进行比较，确定复合数据集与数据集之间的相关程度。 复合数据集内的数据点被选择性地加权以提高相关度，并且上述步骤被选择性地迭代地重复，直到相关度至少为期望值为止。 选择性地确定复合数据集内的数据点的残差。 在第一指定范围内加权的复合数据集内的加权数据点中的至少一个以及在第二指定范围内具有残差的复合数据集内的数据点被选择性地输出为异常值数据点。
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公开(公告)号：US07598127B2
公开(公告)日：2009-10-06
申请号：US11284503
申请日：2005-11-22
IPC分类号： H01L21/86
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , Y10S977/742 , H01L2924/00
摘要： A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer. The photoresist layer is removed, and electrically conductive contacts are formed on each of the two ends of the fuse.
摘要翻译： 通过沉积碳纳米管层形成碳纳米管熔丝，然后在碳纳米管层上直接沉积覆盖层的方法。 盖层由具有不足量的氧的材料形成，以在操作条件下显着地氧化碳纳米管层，否则足够坚固以保护碳纳米管层免受氧气和等离子体的影响。 在盖层上形成光致抗蚀剂层，并且将光致抗蚀剂层图案化以限定所需尺寸的熔丝。 完全蚀刻盖层和碳纳米管层，而不去除光致抗蚀剂层，以限定在碳纳米管层中具有两端的熔丝。 只是盖层被蚀刻，而不去除光致抗蚀剂层，以便在光致抗蚀剂层下的盖层的边缘处将盖层减少所需量，而不损害碳纳米管层。 去除光致抗蚀剂层，并且在熔丝的两端的每一端上形成导电触点。
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公开(公告)号：US07315360B2
公开(公告)日：2008-01-01
申请号：US10949760
申请日：2004-09-24
IPC分类号： G01B1/00
CPC分类号： G01R31/2891 , G01R31/311
摘要： A method for creating a reference for a first position on a substrate edge. A first reference point is selected relative to a circumference of the substrate edge, and a second reference point is selected relative to a bevel of the substrate edge. A first distance along the circumference of the substrate edge between the first reference point and the first position is identified as a first coordinate, and a second distance along the bevel of the substrate edge between the second reference point and the first position is identified as a second coordinate. The first coordinate and the second coordinate are used as the reference for the first position.
摘要翻译： 一种用于为衬底边缘上的第一位置创建参考的方法。 相对于衬底边缘的圆周选择第一参考点，并且相对于衬底边缘的斜面选择第二参考点。 沿着第一参考点和第一位置之间的衬底边缘的圆周的第一距离被识别为第一坐标，并且沿着第二参考点和第一位置之间的衬底边缘的斜面的第二距离被识别为 第二个坐标。 第一坐标和第二坐标用作第一位置的参考。
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公开(公告)号：US06512985B1
公开(公告)日：2003-01-28
申请号：US09574365
申请日：2000-05-19
申请人： Bruce J. Whitefield , Manu Rehani , John A. Knoch
发明人： Bruce J. Whitefield , Manu Rehani , John A. Knoch
IPC分类号： G06F1900
CPC分类号： G05B19/41875 , G05B2219/32201 , G05B2219/32212 , Y02P90/22
摘要： A computerized system for analyzing information associated with a process unit. A database contains historical information relating to previously compiled information. A secure input receives criteria from a restricted source. A computer mathematically determines a limit based upon the criteria. An open input receives the information associated with the process unit from multiple test locations. A compiler selectively adds to the database of historical information the information. The computer also selects at least a portion of the information based upon selection criteria. In addition, the computer manipulates the selected information based upon manipulation criteria. The manipulated information is compared against the limit. An output indicates a first disposition of the process unit when the manipulated information violates the limit. The output indicates a second disposition of the process unit when the manipulated information does not violate the limit.
摘要翻译： 用于分析与处理单元相关联的信息的计算机化系统。 数据库包含与以前编译的信息有关的历史信息。 安全输入从受限源接收标准。 计算机以数学方式根据标准确定极限。 开放输入从多个测试位置接收与处理单元相关联的信息。 编译器选择性地向数据库添加历史信息的信息。 计算机还根据选择标准选择信息的至少一部分。 此外，计算机基于操作标准来操纵所选择的信息。 将操纵的信息与限制进行比较。 输出指示当操纵的信息违反限制时处理单元的第一处置。 当操纵信息不违反限制时，输出表示处理单元的第二处置。
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公开(公告)号：US06645857B1
公开(公告)日：2003-11-11
申请号：US10201010
申请日：2002-07-22
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76877
摘要： A method of forming an electrically conductive via that abuts a key hole formed in filler material. A void is etched through the filler material in which the key hole is formed, thereby forming a link between the void and the key hole. A liner is formed within the void, where the liner is formed to a thickness that is at least about half a minimum cross sectional dimension of the key hole, so as to plug the link between the void and the key hole and thereby trap any contaminants within the key hole. Electrically conductive via material is deposited within the void to form the via.
摘要翻译： 形成与填充材料形成的键孔抵接的导电孔的方法。 通过形成有键孔的填充材料蚀刻空隙，从而在空隙和键孔之间形成连接。 衬垫形成在空隙内，其中衬垫形成为至少约关键孔的最小横截面尺寸的大约一半的厚度，以便堵塞空隙和键孔之间的连接，从而捕获任何污染物 在钥匙孔内。 导电通孔材料沉积在空隙内以形成通孔。
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