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公开(公告)号:US20150137388A1
公开(公告)日:2015-05-21
申请号:US14549518
申请日:2014-11-20
申请人: Eun-Ji KIM , Sung-Dong CHO , Sin-Woo KANG , Myung-Soo JANG , Yeong-Lyeol PARK , Seung-Teak LEE
发明人: Eun-Ji KIM , Sung-Dong CHO , Sin-Woo KANG , Myung-Soo JANG , Yeong-Lyeol PARK , Seung-Teak LEE
IPC分类号: H01L23/522 , H01L23/528
CPC分类号: H01L23/562 , H01L21/76816 , H01L21/76898 , H01L23/481 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2224/13
摘要: A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure.
摘要翻译: 半导体器件包括:第一低k电介质层结构,包括依次层叠在衬底上的至少一个第一低k电介质层,延伸穿过衬底的至少一部分的通孔结构和第一低k电介质层结构, 以及在第一低k电介质层结构中与通孔结构间隔开的第一阻挡层图案结构。 第一阻挡层图案结构围绕第一阻挡层结构的侧壁。
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2.
公开(公告)号:US20120199970A1
公开(公告)日:2012-08-09
申请号:US13361088
申请日:2012-01-30
申请人: Ki-Young Yun , Yeong-Lyeol PARK , Ki-Soon BAE , Woon-Seob LEE , Sung-Dong CHO , Sin-Woo KANG , Sang-Wook JI , Eun-Ji KIM
发明人: Ki-Young Yun , Yeong-Lyeol PARK , Ki-Soon BAE , Woon-Seob LEE , Sung-Dong CHO , Sin-Woo KANG , Sang-Wook JI , Eun-Ji KIM
IPC分类号: H01L23/498 , H01L21/768
CPC分类号: H01L23/5226 , H01L21/76816 , H01L21/76898 , H01L23/481 , H01L2224/13025 , H01L2224/16146
摘要: A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.
摘要翻译: 半导体器件包括具有通孔区域和电路区域的衬底,形成在衬底顶表面上的绝缘夹层,具有第一表面和第二表面的通孔,其中贯穿电极穿透衬底的通孔区域 并且所述第二表面与所述基板的底面基本共面;形成在所述贯通电极的第一表面的一部分上的第一上布线,形成在所述第一上布线的顶表面的一部分上的多个通孔接头 以及形成在所述多个通孔接触件上的第二上部布线。
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