公开(公告)号：US20120056330A1

公开(公告)日：2012-03-08

申请号：US13186049

申请日：2011-07-19

申请人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

发明人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

摘要翻译： 半导体器件可以包括衬底和通孔。 衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。 贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞 以便连接到第一插头。

公开(公告)号：US08729684B2

公开(公告)日：2014-05-20

申请号：US13215425

申请日：2011-08-23

申请人： Yeong-Lyeol Park ,  Sung-Dong Cho ,  Sin-Woo Kang

发明人： Yeong-Lyeol Park ,  Sung-Dong Cho ,  Sin-Woo Kang

IPC分类号： H01L23/02

CPC分类号： H01L22/34 ,  H01L23/49541 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/0268 ,  H05K7/1053 ,  H05K2201/10378

摘要： An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.

摘要翻译： 插入器芯片可以包括基板，多个上端子，多个下端子，将第一上端子电连接到第一组一个或多个下端子的第一导电图案，电连接 第二上端子连接到第二组一个或多个下端子，以及设置在第一导电图案和第二导电图案之间的切割测试图案，用于测试第一导电图案和第二导电图案的电特性的测试图案。

公开(公告)号：US20120199970A1

公开(公告)日：2012-08-09

申请号：US13361088

申请日：2012-01-30

申请人： Ki-Young Yun ,  Yeong-Lyeol PARK ,  Ki-Soon BAE ,  Woon-Seob LEE ,  Sung-Dong CHO ,  Sin-Woo KANG ,  Sang-Wook JI ,  Eun-Ji KIM

发明人： Ki-Young Yun ,  Yeong-Lyeol PARK ,  Ki-Soon BAE ,  Woon-Seob LEE ,  Sung-Dong CHO ,  Sin-Woo KANG ,  Sang-Wook JI ,  Eun-Ji KIM

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/16146

摘要： A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

摘要翻译： 半导体器件包括具有通孔区域和电路区域的衬底，形成在衬底顶表面上的绝缘夹层，具有第一表面和第二表面的通孔，其中贯穿电极穿透衬底的通孔区域 并且所述第二表面与所述基板的底面基本共面;形成在所述贯通电极的第一表面的一部分上的第一上布线，形成在所述第一上布线的顶表面的一部分上的多个通孔接头 以及形成在所述多个通孔接触件上的第二上部布线。

公开(公告)号：US20150137388A1

公开(公告)日：2015-05-21

申请号：US14549518

申请日：2014-11-20

申请人： Eun-Ji KIM ,  Sung-Dong CHO ,  Sin-Woo KANG ,  Myung-Soo JANG ,  Yeong-Lyeol PARK ,  Seung-Teak LEE

发明人： Eun-Ji KIM ,  Sung-Dong CHO ,  Sin-Woo KANG ,  Myung-Soo JANG ,  Yeong-Lyeol PARK ,  Seung-Teak LEE

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/562 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2224/13

摘要： A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure.

摘要翻译： 半导体器件包括：第一低k电介质层结构，包括依次层叠在衬底上的至少一个第一低k电介质层，延伸穿过衬底的至少一部分的通孔结构和第一低k电介质层结构， 以及在第一低k电介质层结构中与通孔结构间隔开的第一阻挡层图案结构。 第一阻挡层图案结构围绕第一阻挡层结构的侧壁。

公开(公告)号：US08836109B2

公开(公告)日：2014-09-16

申请号：US13361088

申请日：2012-01-30

申请人： Ki-Young Yun ,  Yeong-Lyeol Park ,  Ki-Soon Bae ,  Woon-Seob Lee ,  Sung-Dong Cho ,  Sin-Woo Kang ,  Sang-Wook Ji ,  Eun-Ji Kim

发明人： Ki-Young Yun ,  Yeong-Lyeol Park ,  Ki-Soon Bae ,  Woon-Seob Lee ,  Sung-Dong Cho ,  Sin-Woo Kang ,  Sang-Wook Ji ,  Eun-Ji Kim

IPC分类号： H01L23/053 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/16146

摘要： A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.

摘要翻译： 半导体器件包括具有通孔区域和电路区域的衬底，形成在衬底顶表面上的绝缘夹层，具有第一表面和第二表面的通孔，其中贯穿电极穿透衬底的通孔区域 并且所述第二表面与所述基板的底面基本共面;形成在所述贯通电极的第一表面的一部分上的第一上布线，形成在所述第一上布线的顶表面的一部分上的多个通孔接头 以及形成在所述多个通孔接触件上的第二上部布线。

公开(公告)号：US08592988B2

公开(公告)日：2013-11-26

申请号：US13186049

申请日：2011-07-19

申请人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

发明人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

摘要翻译： 半导体器件可以包括衬底和通孔。 衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。 贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞 以便连接到第一插头。

公开(公告)号：US20120051019A1

公开(公告)日：2012-03-01

申请号：US13215425

申请日：2011-08-23

申请人： Yeong-Lyeol Park ,  Sung-Dong Cho ,  Sin-Woo Kang

发明人： Yeong-Lyeol Park ,  Sung-Dong Cho ,  Sin-Woo Kang

IPC分类号： H05K7/06 ,  H05K3/22 ,  H01L21/50

CPC分类号： H01L22/34 ,  H01L23/49541 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/09181 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/0268 ,  H05K7/1053 ,  H05K2201/10378

摘要： An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.

摘要翻译： 插入器芯片可以包括基板，多个上端子，多个下端子，将第一上端子电连接到第一组一个或多个下端子的第一导电图案，电连接 第二上端子连接到第二组一个或多个下端子，以及设置在第一导电图案和第二导电图案之间的切割测试图案，用于测试第一导电图案和第二导电图案的电特性的测试图案。