公开(公告)号：US20070048938A1

公开(公告)日：2007-03-01

申请号：US11431626

申请日：2006-05-10

申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim ,  Yong-lack Choi

发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim ,  Yong-lack Choi

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66795

摘要： A method of manufacturing a MOS transistor with a multiple channel structure prevents damage to and loss of material of a channel region. The method includes: forming a stacked structure including a plurality of first material layers and a plurality of second material layers that have different etching selectivities and are alternately stacked on a semiconductor substrate; forming an active mask on a portion of the stacked structure, the active mask defining an active region; etching regions of the stacked structure to expose sidewalls of the stacked structure; forming a plurality of tunnels by selectively removing the first material layer between the exposed sidewalls of the stacked structure; removing the active mask; and forming a gate electrode on the active region to fill the plurality of tunnels.

摘要翻译： 制造具有多通道结构的MOS晶体管的方法防止了沟道区的材料损坏和损失。 该方法包括：形成包括多个第一材料层和多个具有不同蚀刻选择性的第二材料层并交替堆叠在半导体衬底上的层叠结构; 在所述堆叠结构的一部分上形成有源掩模，所述有源掩模限定有源区; 蚀刻所述堆叠结构的区域以暴露所述堆叠结构的侧壁; 通过选择性地去除所述堆叠结构的暴露的侧壁之间的第一材料层来形成多个隧道; 去除活性面膜; 以及在所述有源区上形成栅电极以填充所述多个隧道。

公开(公告)号：US08129800B2

公开(公告)日：2012-03-06

申请号：US11374644

申请日：2006-03-13

申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

IPC分类号： H01L29/06

CPC分类号： H01L29/78696 ,  H01L29/42392

摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。

公开(公告)号：US20070045725A1

公开(公告)日：2007-03-01

申请号：US11374644

申请日：2006-03-13

申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L29/42392

摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。

公开(公告)号：US08835993B2

公开(公告)日：2014-09-16

申请号：US13411699

申请日：2012-03-05

申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/423

CPC分类号： H01L29/78696 ,  H01L29/42392

摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。

公开(公告)号：US20060192249A1

公开(公告)日：2006-08-31

申请号：US11396488

申请日：2006-04-03

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US07972914B2

公开(公告)日：2011-07-05

申请号：US12477348

申请日：2009-06-03

申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/338 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法。

公开(公告)号：US20060231907A1

公开(公告)日：2006-10-19

申请号：US11403986

申请日：2006-04-13

申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided,

摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法，

公开(公告)号：US20060175669A1

公开(公告)日：2006-08-10

申请号：US11339126

申请日：2006-01-25

申请人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

摘要： Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

摘要翻译： 提供了包括具有金属栅极的FinFET的半导体器件及其制造方法。 半导体器件包括：形成在半导体衬底中并从半导体衬底的表面突出的有源区; 翅片，其包括由有源区域的表面形成的第一和第二突起，并且基于形成在有源区域中的中心沟槽并且使用第一和第二突起的上表面和侧面作为沟道区域彼此平行; 形成在包括所述鳍片的所述有源区域上的栅极绝缘层; 形成在所述栅极绝缘层上的金属栅电极; 形成在所述金属栅电极的侧壁上的栅极间隔; 以及在金属栅电极的两侧旁边的有源区域中形成的源极和漏极。 这里，金属栅电极包括与栅极间隔物和栅极绝缘层接触的阻挡层和形成在阻挡层上的金属层。

公开(公告)号：US08168492B2

公开(公告)日：2012-05-01

申请号：US12754128

申请日：2010-04-05

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US20090239346A1

公开(公告)日：2009-09-24

申请号：US12477348

申请日：2009-06-03

申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法。