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    Management of cache memory in a flash cache architecture
    1.
    发明授权
    Management of cache memory in a flash cache architecture 有权
    在闪存缓存架构中管理缓存内存

    公开(公告)号：US09135181B2

    公开(公告)日：2015-09-15

    申请号：US13280869

    申请日：2011-10-25

    申请人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    发明人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0888 ,  G06F12/0246

    摘要： A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.

    摘要翻译： 一种用于在闪存缓存架构中管理高速缓存存储器的方法。 该方法包括提供存储高速缓存控制器，至少包括闪存控制器的闪速存储器，以及至少后端存储设备，并且维护读取高速缓存元数据，用于跟踪要读取的闪速存储器缓存的数据，以及写入用于跟踪的高速缓存元数据 闪存数据预计将被缓存。

    Operating a Data Storage System
    2.
    发明申请
    Operating a Data Storage System 有权
    操作数据存储系统

    公开(公告)号：US20120131381A1

    公开(公告)日：2012-05-24

    申请号：US13387740

    申请日：2010-08-05

    申请人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadis

    发明人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadis

    IPC分类号： G06F11/20

    CPC分类号： G06F3/0647 ,  G06F3/0616 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7208 ,  G06F2212/7211

    摘要： A data storage system including at least one memory device array including memory devices for storing data; and a storage subsystem controller for performing a method for operating the memory devices within the memory device array by relocating parity entities from a first memory device to a spare memory device replacing a failed memory device, and by storing one or more of reconstructed data entities on the first memory device.

    摘要翻译： 一种数据存储系统，包括至少一个存储器件阵列，其包括用于存储数据的存储器件; 以及存储子系统控制器，用于通过将奇偶校验实体从第一存储器设备重新定位到替换故障存储器设备的备用存储器设备，以及通过将一个或多个重构数据实体存储在存储设备阵列中来执行操作存储器设备的方法 第一个存储设备。

    MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE
    3.
    发明申请
    MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE 有权
    闪存高速缓存架构中的高速缓存存储器管理

    公开(公告)号：US20120110247A1

    公开(公告)日：2012-05-03

    申请号：US13280869

    申请日：2011-10-25

    申请人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    发明人： Evangelos Stavros Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0888 ,  G06F12/0246

    摘要： A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.

    摘要翻译： 一种用于在闪存缓存架构中管理高速缓冲存储器的方法。 该方法包括提供存储高速缓存控制器，至少包括闪存控制器的闪速存储器，以及至少后端存储设备，并且维护读取高速缓存元数据，用于跟踪要读取的闪速存储器缓存的数据，以及写入用于跟踪的高速缓存元数据 闪存数据预计将被缓存。

    MODEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR SELECTING AN OPTIMUM DATA RATE USING ERROR SIGNALS REPRESENTING THE DIFFERENCE BETWEEN THE OUTPUT OF AN EQUALIZER AND THE OUTPUT OF A SLICER OR DETECTOR
    7.
    发明授权
    MODEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR SELECTING AN OPTIMUM DATA RATE USING ERROR SIGNALS REPRESENTING THE DIFFERENCE BETWEEN THE OUTPUT OF AN EQUALIZER AND THE OUTPUT OF A SLICER OR DETECTOR 失效
    使用错误信号选择最佳数据速率的方式，方法和计算机程序产品，表示均衡器的输出与切换器或检测器的输出之间的差异

    公开(公告)号：US06665336B2

    公开(公告)日：2003-12-16

    申请号：US10428357

    申请日：2003-05-02

    申请人： Youssef Abdelilah ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Ajay Dholakia ,  Evangelos Stavros Eleftheriou ,  Dongming Hwang ,  Fredy D. Neeser ,  Malcolm Scott Ware ,  Hua Ye

    发明人： Youssef Abdelilah ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Ajay Dholakia ,  Evangelos Stavros Eleftheriou ,  Dongming Hwang ,  Fredy D. Neeser ,  Malcolm Scott Ware ,  Hua Ye

    IPC分类号： H04B1700

    CPC分类号： H04L1/0021 ,  H04L1/0002 ,  H04L25/03057 ,  H04L25/4927 ,  H04L2025/03388 ,  Y02D50/10

    摘要： Modems, methods, and computer program products select a data rate based on error signals in a modem. In an illustrative embodiment, error signals representing the difference between an output of an equalizer and an output of a detector are accumulated and an average error value is computed therefrom. A signal to noise ratio is determined using the average error value. The signal to noise ratio is then used to select a data rate. In another illustrative embodiment, the mean squared error at the output of the equalizer is determined and then used, along with the probability of error in correctly detecting a symbol, to select a data rate. Incorrect decisions in detecting received data symbols can cause a catastrophic failure in a decision feedback equalizer used in a modem receiver as errors are repeatedly fed back causing the tap coefficients for the equalizer filters to be shifted from their normal operating values. By adjusting the data rate in accordance with the error signals generated in a modem receiver, the decision feedback equalizer can operate with greater stability as the data rate can be reduced in response to increased noise conditions.

    摘要翻译： 调制解调器，方法和计算机程序产品根据调制解调器中的错误信号选择数据速率。 在说明性实施例中，代表均衡器的输出和检测器的输出之间的差的误差信号被累加，并且从其计算出平均误差值。 使用平均误差值确定信噪比。 然后使用信噪比来选择数据速率。 在另一说明性实施例中，确定均衡器的输出处的均方误差，然后与正确检测符号的误差概率一起使用以选择数据速率。 检测接收到的数据符号时的不正确决定可能导致在调制解调器接收机中使用的判决反馈均衡器中的灾难性故障，因为错误被反复反馈，导致均衡器滤波器的抽头系数从其正常操作值偏移。 通过根据在调制解调器接收机中产生的误差信号来调整数据速率，当响应于增加的噪声条件可以减小数据速率时，判决反馈均衡器可以更稳定地工作。

    Receivers, methods, and computer program products for an analog modem that receives data signals from a digital modem
    9.
    发明授权
    Receivers, methods, and computer program products for an analog modem that receives data signals from a digital modem 失效
    用于从数字调制解调器接收数据信号的模拟调制解调器的接收器，方法和计算机程序产品

    公开(公告)号：US07003030B2

    公开(公告)日：2006-02-21

    申请号：US10635194

    申请日：2003-08-06

    申请人： Youssef Abdelilah ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Ajay Dholakia ,  Evangelos Stavros Eleftheriou ,  Robert F. H. Fischer ,  Dongming Hwang ,  Fredy D. Neeser ,  Malcolm Scott Ware ,  Hua Ye

    发明人： Youssef Abdelilah ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Ajay Dholakia ,  Evangelos Stavros Eleftheriou ,  Robert F. H. Fischer ,  Dongming Hwang ,  Fredy D. Neeser ,  Malcolm Scott Ware ,  Hua Ye

    IPC分类号： H03K5/159

    CPC分类号： H04L7/0062 ,  H04L7/0029 ,  H04L2025/03363 ,  H04L2025/0342 ,  H04L2025/0349

    摘要： Receivers, methods, and computer program products can be used to demodulate a data signal transmitted from a digital source, which has a network sampling rate that is synchronized with a network clock. In an illustrative embodiment, a receiver includes a two-stage interpolator that receives digital samples of the data signal as an input and produces an interpolated digital sample stream to be filtered by an adaptive fractionally spaced decision feedback equalizer. The digital samples received in the interpolator are synchronized with a local clock; however, the interpolated sample stream is synchronized with the network clock. A slicer generates symbols for the samples output from the decision feedback equalizer by comparing the samples with a reference signaling alphabet. The receiver can be used in a V.90 client modem to demodulate pulse code modulated (PCM) data transmitted as pulse amplitude modulated (PAM) signals from a digital network. In addition, the receiver is compatible with legacy analog modem front ends and transmitters. The two-stage interpolator allows the timing synchronization to be performed with extremely fine granularity, which can be useful in PCM modems that typically require relatively high signal to noise ratios.

    摘要翻译： 接收器，方法和计算机程序产品可用于解调从具有与网络时钟同步的网络采样速率的数字源发送的数据信号。 在说明性实施例中，接收机包括二阶插值器，其接收作为输入的数据信号的数字样本，并产生经过自适应分数间隔的判决反馈均衡器滤波的内插数字样本流。 在内插器中接收的数字样本与本地时钟同步; 然而，插值的采样流与网络时钟同步。 切片器通过将样本与参考信号字母表进行比较来生成从判决反馈均衡器输出的样本的符号。 接收机可用于V.90客户端调制解调器中，以解调从数字网络传输的脉冲编码调制（PCM）数据作为脉冲幅度调制（PAM）信号。 此外，接收机与传统模拟调制解调器前端和发射机兼容。 两级内插器允许以非常精细的粒度执行定时同步，这在通常需要相对较高的信噪比的PCM调制解调器中是有用的。