公开(公告)号：US11651807B2

公开(公告)日：2023-05-16

申请号：US17113595

申请日：2020-12-07

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1657

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US12165684B2

公开(公告)日：2024-12-10

申请号：US18297793

申请日：2023-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

IPC: G11C11/16

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US10658013B2

公开(公告)日：2020-05-19

申请号：US16252067

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Frederick Neumeyer

IPC: G11C5/14 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  G11C29/02 ,  G11C29/50

Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.