公开(公告)号：US20210328138A1

公开(公告)日：2021-10-21

申请号：US17270151

申请日：2019-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin DESHPANDE ,  Kerry NAGEL ,  Santosh KARRE

IPC: H01L43/12 ,  H01L43/02

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

公开(公告)号：US20220336734A1

公开(公告)日：2022-10-20

申请号：US17659234

申请日：2022-04-14

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Santosh KARRE

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.

公开(公告)号：US20240306513A1

公开(公告)日：2024-09-12

申请号：US18664928

申请日：2024-05-15

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin DESHPANDE ,  Kerry NAGLE ,  Santosh KARRE

IPC: H10N50/01 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10N50/80 ,  H01F10/3254 ,  H01F10/3272 ,  H10B61/00

Abstract: A magnetoresistive element may include a via providing an electrical connection between one or more metal regions and magnetoresistive devices. The via may include a transition metal layer, a tantalum-rich layer, and/or a cap layer. The transition metal layer may be formed by atomic layer deposition. Additionally, one or more layers of the via may be formed in the trench etched in one or more interlevel dielectric layers. The via may have an aspect ratio less than or equal to 2. The via may have a diameter less than or equal than a diameter of the magnetoresistive device electrically connected to one or more metal regions by the via.