公开(公告)号：US20220336734A1

公开(公告)日：2022-10-20

申请号：US17659234

申请日：2022-04-14

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Santosh KARRE

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.

公开(公告)号：US20200075843A1

公开(公告)日：2020-03-05

申请号：US16561418

申请日：2019-09-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry NAGEL ,  Sanjeev AGGARWAL

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.

公开(公告)号：US20210408371A1

公开(公告)日：2021-12-30

申请号：US17468896

申请日：2021-09-08

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason JANESKY

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20210249589A1

公开(公告)日：2021-08-12

申请号：US16783740

申请日：2020-02-06

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Hamid ALMASI ,  SHIMON ,  Kerry NAGEL ,  Han Kyu LEE

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/02

Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.

公开(公告)号：US20210328138A1

公开(公告)日：2021-10-21

申请号：US17270151

申请日：2019-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin DESHPANDE ,  Kerry NAGEL ,  Santosh KARRE

IPC: H01L43/12 ,  H01L43/02

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

公开(公告)号：US20200185602A1

公开(公告)日：2020-06-11

申请号：US16794449

申请日：2020-02-19

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20190157550A1

公开(公告)日：2019-05-23

申请号：US16255912

申请日：2019-01-24

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason Janesky

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.