公开(公告)号：US20170054009A1

公开(公告)日：2017-02-23

申请号：US15242018

申请日：2016-08-19

申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.

发明人： Kwang-won LEE ,  Hye-min KANG ,  Jae-gil LEE

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L21/324 ,  H01L29/36 ,  H01L29/66 ,  H01L21/266

CPC分类号： H01L29/7395 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66333

摘要： A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

摘要翻译： 超结半导体器件包括掺杂有第一导电类型的第一半导体层; 形成在所述第一半导体层上的有源区，所述有源区包括漂移层; 以及设置成围绕所述有源区域的端接区域，所述端接区域包括设置在所述漂移层的侧表面上的下边缘区域和设置在所述下边缘区域上的上边缘区域，其中所述上边缘区域包括较低的电荷平衡 所述下电荷平衡区具有不同于所述第一导电类型的第二导电类型，以及设置在所述下电荷平衡区上的上电荷平衡区，所述上电荷平衡区具有第一导电类型。

公开(公告)号：US20140141584A1

公开(公告)日：2014-05-22

申请号：US14165187

申请日：2014-01-27

申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.

发明人： Jin-myung KIM ,  Se-woong OH ,  Jae-gil LEE ,  Young-chul CHOI ,  Ho-cheol JANG

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

摘要： A power semiconductor device includes: a drain region of a first conductive type; a drift region of a first conductive type formed on the drain region; a first body region of a second conductive type formed below an upper surface of the drift region; a second body region of a second conductive type formed below the upper surface of the drift region and in the first body region; a third body region of a second conductive type formed by protruding downwards from a lower end of the first body region; a source region of a first conductive type formed below the upper surface of the drift region and in the first body region; and a gate insulating layer formed on channel regions of the first body region and on the drift region between the first body regions.

摘要翻译： 功率半导体器件包括：第一导电类型的漏极区域; 形成在漏区上的第一导电类型的漂移区; 形成在所述漂移区域的上表面下方的第二导电类型的第一体区; 第二导电类型的第二体区，形成在所述漂移区的上表面下方和所述第一体区中; 第二导电类型的第三体区域，从第一体区域的下端向下突出形成; 形成在所述漂移区域的上表面下方的所述第一导电类型的源极区域和所述第一体区域中; 以及栅极绝缘层，形成在第一体区的沟道区域和第一体区之间的漂移区上。