公开(公告)号：US20210335440A1

公开(公告)日：2021-10-28

申请号：US17243304

申请日：2021-04-28

Applicant: FLC Technology Group, Inc.

Inventor： Jiapeng Guo ,  Hunglin Hsu ,  Cheng Chung Wang ,  Xin Song ,  Xi Zhu ,  Sehat Sutardja

IPC: G11C29/36 ,  G11C29/16 ,  G11C29/44

Abstract: A memory test system including a memory storing non-transitory machine executable instructions configured to generate test patterns. A processor or state machine is configured to execute the machine executable instructions to generate the test patterns. A memory controller receives the test patterns, writes the generated test patterns to a memory being tested, and reads the test patterns from the memory being tested to create read test patterns. A comparator or controller is configured to compare the generated test patterns to the read test patterns and responsive to differences between the generated test patterns and the read test patterns, generate a memory read error. Pass/fail registers may store data and a memory address associated with the memory read error. The test patterns can be stored for a period of time before being read to test the ability of the memory being tested to store the test pattern.

公开(公告)号：US20190384709A1

公开(公告)日：2019-12-19

申请号：US16444556

申请日：2019-06-18

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/1009 ,  G06F9/38 ,  G06F9/50

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US20210334158A1

公开(公告)日：2021-10-28

申请号：US17243172

申请日：2021-04-28

Applicant: FLC Technology Group, Inc.

Inventor： Xiaojue Zeng ,  Cheng Chung Wang ,  Fan Yang ,  Rong Xu ,  Bo Hu ,  Hunglin Hsu ,  Sehat Sutardja

IPC: G06F11/10 ,  G06F11/30 ,  G06F12/02 ,  G06F13/16

Abstract: A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.

公开(公告)号：US20210173779A1

公开(公告)日：2021-06-10

申请号：US17180530

申请日：2021-02-19

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0846 ,  G06F12/1009 ,  G06F12/0897

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US10936492B2

公开(公告)日：2021-03-02

申请号：US16444556

申请日：2019-06-18

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0897 ,  G06F12/0811 ,  G06F12/0846 ,  G06F9/50 ,  G06F9/38 ,  G06F12/1009

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US20230153243A1

公开(公告)日：2023-05-18

申请号：US18094228

申请日：2023-01-06

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F9/50 ,  G06F9/38 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F12/0851 ,  G06F9/5077 ,  G06F9/3816 ,  G06F12/1009 ,  G06F12/0897

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US11645148B2

公开(公告)日：2023-05-09

申请号：US17243172

申请日：2021-04-28

Applicant: FLC Technology Group, Inc.

Inventor： Xiaojue Zeng ,  Cheng Chung Wang ,  Fan Yang ,  Rong Xu ,  Bo Hu ,  Hunglin Hsu ,  Sehat Sutardja

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/30 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F11/1064 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0238 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/403

Abstract: A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.

公开(公告)号：US20240394201A1

公开(公告)日：2024-11-28

申请号：US18671871

申请日：2024-05-22

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F13/16 ,  G06F12/0811 ,  G06F13/42

Abstract: A cable for use between a host and an external memory. The cable has a first and second ends and two or more electrically conductive conductors, surrounded by an insulator, extending from the first to the second end. At the first end is a first cable connector that is electrically connected to the conductors and physically connected to the insulator. The first cable connector connects to an external memory. A second cable connector, at the second end, is electrically connected to the conductors and physically connected to the insulator. The second cable connector connects to a host. A final level cache (FLC) system, in the second cable connector, comprises a connector memory with associated controller configured to store data, and a FLC controller with memory. The FLC controller stores memory addresses that correspond to data stored in the connector memory and operates the connector memory as a cache memory.

公开(公告)号：US20240394200A1

公开(公告)日：2024-11-28

申请号：US18669389

申请日：2024-05-20

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F13/16 ,  G06F12/0811 ,  G06F13/40

Abstract: A memory system, operating under the HBM standard, comprising a memory stack having layers of memory dies, on a base die. The base die is in communication with the memory stack and further comprises final level cache (FLC) controller. The FLC controller configured to receive the data request for requested data from a requesting element and process the data request to determine if the requested data is stored in the memory stack. Responsive to the requested data being stored in the memory stack, retrieve the requested data from the memory stack, transmit the requested data to the processor, and update a recently used tag associated with the requested data. Responsive to the requested data not being stored in the memory stack, the final level cache controller retrieves the requested data from an external memory, transmits the requested data to the processor, and stores the requested data in the memory stack.

公开(公告)号：US20230144038A1

公开(公告)日：2023-05-11

申请号：US17985686

申请日：2022-11-11

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/10

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/10 ,  G06F2212/603

Abstract: A data storage and access system for use with a processor having processor cache such that the processor is configured generate a data request for data which is provided to a final level cache (FLC) cache system that is configured to function as main memory and receive the data request. The FLC cache system comprising a first FLC module configured to process the data request from the processor. A second FLC module, responsive to the first FLC module not having the data requested by the processor, receives and processes the data request from the first FLC module. A switch accessible memory, which connects through a switch to the second FLC module, is configured to receive the data request responsive to the second FLC module not having the data. The switch accessible memory may be shared by additional FLC cache systems as a shared memory pool.