SEMICONDUCTOR PATTERNING
    2.
    发明申请

    公开(公告)号:US20210118912A1

    公开(公告)日:2021-04-22

    申请号:US16463670

    申请日:2017-11-28

    摘要: A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.

    CROSS-LINKED POLYMERS
    4.
    发明申请

    公开(公告)号:US20200238332A1

    公开(公告)日:2020-07-30

    申请号:US16493574

    申请日:2018-03-14

    摘要: A technique comprising: depositing a first layer comprising a precursor to a cross-linked polymer on a substrate comprising at least a semiconductor material that provides one or more semiconductor channels for one or more transistors, wherein said first layer provides at least part of a gate dielectric for said one or more transistors; and exposing the first layer to an argon plasma to produce the cross-linked polymer from the precursor.