公开(公告)号：US20180039589A1

公开(公告)日：2018-02-08

申请号：US15227834

申请日：2016-08-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： HEMANT NAUTIYAL ,  RAJAN KAPOOR ,  ARVIND KAUSHIK ,  PUNEET KHANDELWAL

IPC: G06F13/24 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/4286 ,  Y02D10/14 ,  Y02D10/151

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

公开(公告)号：US20170181192A1

公开(公告)日：2017-06-22

申请号：US14975831

申请日：2015-12-20

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： GIRRAJ K. AGRAWAL ,  ARVIND KAUSHIK ,  VINCENT MARTINEZ ,  AMRIT P. SINGH

IPC: H04W74/08 ,  H04W72/12

CPC classification number: H04W74/0833 ,  H04L25/00 ,  H04W72/1284

Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

公开(公告)号：US20170063346A1

公开(公告)日：2017-03-02

申请号：US14841712

申请日：2015-09-01

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Akshat Mittal ,  ARVIND KAUSHIK ,  PETER Z. RASHEV ,  AMRIT P. SINGH

IPC: H03H17/06

CPC classification number: H03H17/06 ,  H03H17/0225 ,  H03H17/0294

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Abstract translation: FIR滤波器包括段单元，每个单元可配置为内插滤波器，抽取滤波器，对称滤波器或非对称滤波器。 两个或多个段单元可配置为级联以形成内插滤波器，抽取滤波器，对称滤波器，非对称滤波器，复对称滤波器或复合非对称滤波器。 FIR滤波器包括对应于段单元的寄存器，用于存储相应段单元的系数值。 FIR滤波器还包括对应于用于产生控制信号的段小区的控制电路。

公开(公告)号：US20180020468A1

公开(公告)日：2018-01-18

申请号：US15213364

申请日：2016-07-18

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： SOMVIR DAHIYA ,  ARVIND KAUSHIK ,  AVIEL LIVAY ,  AMRIT P. SINGH

IPC: H04W72/12 ,  H04L25/05

CPC classification number: H04L25/05 ,  H04J15/00 ,  H04L1/00 ,  H04L25/00 ,  H04W72/1263

Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.