公开(公告)号：US20140289208A1

公开(公告)日：2014-09-25

申请号：US14180436

申请日：2014-02-14

Applicant: FUJITSU LIMITED

Inventor： Noriko Itani ,  Yasuhiko Nakano ,  Takumi Maruyama ,  RYUJI KAN ,  Shigeki Itou

IPC: H03M7/30

CPC classification number: H03M7/6017 ,  H03M7/3086

Abstract: In a data compression apparatus, a search unit examines the sequence of symbols in compression target data, and searches for a second symbol string having the same sequence of symbols as a first symbol string that occurred previously, and a code generation unit encodes the second symbol string into a code containing information that specifies a block to which the beginning of the first symbol string belongs. In a data decompression apparatus, a code acquisition unit sequentially acquires codes from the beginning of the compressed data, and when the code of the second symbol string is acquired, a decompression unit acquires, from a storage device, one or more blocks starting with a block to which the beginning of the decompressed first symbol string belongs, on the basis of the information contained in the acquired code, and decompresses the second symbol string.

Abstract translation: 在数据压缩装置中，搜索单元检查压缩目标数据中的符号序列，并且搜索具有与之前发生的第一符号串相同的符号序列的第二符号串，并且代码生成单元对第二符号进行编码 字符串转换为包含指定第一个符号字符串开头所属的块的信息的代码。 在数据解压缩装置中，代码获取单元从压缩数据的开始顺序地获取代码，并且当获取第二符号串的代码时，解压缩单元从存储装置获取一个或多个从 基于所获取的代码中包含的信息，解压缩的第一符号串的开头所属的块，解压缩第二符号串。

公开(公告)号：US20160173127A1

公开(公告)日：2016-06-16

申请号：US15053022

申请日：2016-02-25

Applicant: FUJITSU LIMITED

Inventor： Noriko Itani ,  Takumi Maruyama ,  RYUJI KAN ,  Shigeki Itou ,  Yasuhiko Nakano

IPC: H03M7/30

CPC classification number: H03M7/6011 ,  H03M7/3086 ,  H03M7/6017

Abstract: A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string after a first character string in a character string of data before compression that is stored in the memory, the second character string being identical with the first character string, and identifies a length of the matching string, and a relative position indicating how many addresses the first character string precedes the second character string by. The processor extracts a third character string having a length that is less than the relative position from the extracted second character string. The processor encodes a length of the third character string. The processor encodes the relative position.

Abstract translation: 数据压缩装置包括存储器和处理器。 处理器在存储在存储器中的压缩前的数据的字符串中的第一字符串之后的字符串中提取第二字符串作为匹配字符串，第二字符串与第一字符串相同，并且识别 匹配字符串的长度，以及指示第一字符串在第二字符串之前的地址多少的相对位置。 处理器从提取的第二字符串中提取具有小于相对位置的长度的第三字符串。 处理器编码第三个字符串的长度。 处理器编码相对位置。

公开(公告)号：US20160350075A1

公开(公告)日：2016-12-01

申请号：US15093797

申请日：2016-04-08

Applicant: FUJITSU LIMITED

Inventor： Kouji KIMURA ,  RYUJI KAN

IPC: G06F7/501 ,  G06F7/575

CPC classification number: G06F7/575

Abstract: An adder-subtractor includes a first XOR circuit that inverts or non-inverts data from a second input line; first and second operand registers that hold outputs of first and second input selector; a result register that holds the operation result in response to the clock; and an adder that outputs an operation result of first and second input data in the first and second operand registers to the result register and also to inputs of the first and second input selectors via the first bypass line. The adder includes a second XOR circuit for the first and second input data, a carry calculation unit that calculates carry data of the first and second input data, a fourth XOR circuit that inverts or not an output of the second XOR circuit, and a third XOR circuit for outputs of the carry calculation unit and outputs the operation result.

Abstract translation: 加法器 - 减法器包括：第一异或电路，用于对来自第二输入线的数据进行反相或非反相; 保持第一和第二输入选择器的输出的第一和第二操作数寄存器; 一个结果寄存器，保存响应时钟的操作结果; 以及加法器，其将第一和第二操作数寄存器中的第一和第二输入数据的运算结果输出到结果寄存器，以及经由第一旁路线输入第一和第二输入选择器的输入。 所述加法器包括用于所述第一和第二输入数据的第二异或电路，计算所述第一和第二输入数据的进位数据的进位计算单元，反转或不转换所述第二异或电路的输出的第四异或电路， 输入运算单元的XOR电路，输出运算结果。

公开(公告)号：US20150089180A1

公开(公告)日：2015-03-26

申请号：US14464808

申请日：2014-08-21

Applicant: FUJITSU LIMITED

Inventor： Shuji Yamamura ,  Masaharu Maruyama ,  Toshio Yoshida ,  RYUJI KAN ,  NAOHIRO KIYOTA ,  Mikio Hondo ,  TSUYOSHI MOTOKURUMADA

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/023 ,  G06F9/30043 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1441 ,  G06F12/1483

Abstract: An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.

Abstract translation: 一种算术处理装置，具有分配单元，其被配置为在存储器中保留存储器分配区域，并且响应于请求的存储器区域分配函数的执行而将指示地址范围表中的存储器分配区域的地址范围的地址范围信息 存储区域分配，以及确定单元，被配置为参考地址范围表，并且执行关于存储器访问指令的访问目的地地址是否在由地址范围中注册的地址范围信息指示的地址范围内的确定处理 响应于与存储器分配区域相关的存储器访问指令的执行。