公开(公告)号：US11023281B2

公开(公告)日：2021-06-01

申请号：US15964424

申请日：2018-04-27

Applicant: FUJITSU LIMITED

Inventor： Ryosuke Kokubo ,  Tsuyoshi Hashimoto

IPC: G06F9/50 ,  G06F9/48

Abstract: A parallel processing apparatus includes a memory and a processor. The memory stores a program and the processor is coupled to the memory. The processor calculates, based on a number of nodes to be used in execution of respective jobs that are waiting to be executed and a scheduled execution time period for execution of the respective jobs, an execution scale of the respective jobs and allocates the respective jobs to an area in which a number of problem nodes that have a high failure possibility is small from among a plurality of areas into which a region in which a plurality of nodes are disposed is partitioned and divided. The allocation of the jobs is performed in descending order of the execution scale beginning with the job whose execution scale is the largest.

公开(公告)号：US10331489B2

公开(公告)日：2019-06-25

申请号：US15161407

申请日：2016-05-23

Applicant: FUJITSU LIMITED

Inventor： Kazuhiro Matsuyama ,  Tsuyoshi Hashimoto

IPC: G06F9/46 ,  G06F9/50 ,  H04L12/24

Abstract: Computers are connected via multidimensional mesh or torus connection in a network. In response to a request for executing maintenance processing on computers in the network, an apparatus detects execution-scheduled jobs to be executed after an execution start time of the maintenance processing, based on execution-scheduled start times of jobs to be executed by the computers. The apparatus calculates, for each execution-scheduled job, a characteristic value of an axial length of an execution-scheduled job area in each axial direction of multidimensional axes in the network, where the execution-scheduled job area includes a group of computers to execute the each execution-scheduled job. The apparatus determines a maintenance area in the network on which the maintenance processing is to be executed, based on the characteristic values of the axial lengths of the execution-scheduled job areas, and executes the maintenance processing on computers in the maintenance area.

公开(公告)号：US10268529B2

公开(公告)日：2019-04-23

申请号：US15788878

申请日：2017-10-20

Applicant: FUJITSU LIMITED

Inventor： Masaaki Fushimi ,  Tsuyoshi Hashimoto

IPC: G06F9/54 ,  H04L12/861 ,  G06F13/16 ,  G06F13/42 ,  G06F9/48 ,  G06F15/173

Abstract: A first node determines a second node belonging to the same first group as the first node, and creates a first receive buffer corresponding to the second node in a memory. The first node determines a third and a fourth node belonging to a second group, and creates a second receive buffer corresponding to the third node in the memory, without creating a receive buffer corresponding to the fourth node. The first node uses the first receive buffer to receive messages when communicating with the second node, uses the second receive buffer to receive messages when communicating with the third node, and uses the first receive buffer or the second receive buffer to receive messages when communicating with the fourth node.

公开(公告)号：US09847913B2

公开(公告)日：2017-12-19

申请号：US14719360

申请日：2015-05-22

Applicant: FUJITSU LIMITED

Inventor： Hisashi Kanda ,  Tsuyoshi Hashimoto

IPC: G06F15/173 ,  H04L12/24 ,  H04L12/26

CPC classification number: H04L41/0896 ,  H04L43/0817

Abstract: An information gathering system includes: an ID gathering mechanism, provided at a transmitter side node, that generates a collective identifier from one or a plurality of individual identifiers of respective management targets, each of the individual identifiers being generated according to a state of a corresponding management target; and an ID analysis mechanism, provided at a receiver side node, that restores an individual identifier from the collective identifier and specifies a management target based on the restored individual identifier.

公开(公告)号：US09477601B2

公开(公告)日：2016-10-25

申请号：US14694186

申请日：2015-04-23

Applicant: FUJITSU LIMITED

Inventor： Lei Zhang ,  Tsuyoshi Hashimoto

IPC: G06F12/00 ,  G06F12/08 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F12/084 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/0683 ,  G06F9/50 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/6046

Abstract: An apparatus includes a shared cache memory and a controller. The shared cache memory is configured to be divided into sectors by assigning one or more ways to each sector in accordance with a reusability level of data. The controller changes a sector division ratio indicating a ratio between way counts of the divided sectors of the shared cache memory, where the way count is a number of ways assigned to each sector. When first and second jobs are being executed in parallel, in response to a designation of a program of the second job, the controller calculates the sector division ratio, based on data access amount including a size and an access count of data accessed by the first and second jobs and a volume of the shared cache memory, and changes the sector division ratio of the shared cache memory to the calculated sector division ratio.

Abstract translation: 一种装置包括共享高速缓冲存储器和控制器。 共享缓存存储器被配置为根据数据的可重用性级别向每个扇区分配一种或多种方式来划分为扇区。 控制器改变指示共享高速缓冲存储器的分割扇区的路数之间的比率的扇区分频比，其中路径计数是分配给每个扇区的方式的数量。 当并行执行第一和第二作业时，响应于第二作业的程序的指定，控制器基于包括第一和第二作业的数据访问量的数据访问量来计算扇区分割比 和第二作业以及共享高速缓冲存储器的音量，并且将共享高速缓冲存储器的扇区划分比改变为所计算的扇区分割比。

公开(公告)号：US09934036B2

公开(公告)日：2018-04-03

申请号：US14968084

申请日：2015-12-14

Applicant: FUJITSU LIMITED

Inventor： Shunsuke Tanii ,  Tsuyoshi Hashimoto

IPC: G06F9/30 ,  G06F9/45

CPC classification number: G06F9/30058 ,  G06F8/453 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3851

Abstract: A compiler method that performs parallel processing on a data set using multithreading. The method includes calculating a divisor for dividing the data set. The data set is divided into a number of subsets greater than a number of threads. The method generates a plurality of data subsets and executable code. The code performs processing operations and an instruction executed by a first thread that reaches the code. After completing processing operations related to the subsets that have been assigned to the threads, the next subsets are assigned to the threads. When assigning the next subsets, synchronous processing is performed in order to determine which one of “unprocessed”, “processed”, and “assigned to a different thread” is the state of each of the subsets.

公开(公告)号：US09720796B2

公开(公告)日：2017-08-01

申请号：US14812496

申请日：2015-07-29

Applicant: FUJITSU LIMITED

Inventor： Yukio Kozawa ,  Naoki Hayashi ,  Tsuyoshi Hashimoto

IPC: G06F11/10 ,  G06F11/34 ,  G06F11/30 ,  G06F11/20

CPC classification number: G06F11/3466 ,  G06F11/1088 ,  G06F11/2094 ,  G06F11/3034 ,  G06F11/3409

Abstract: An apparatuses includes a processor, a storage unit, and a communication unit to access the storage unit without intermediary of the processor and to access a second apparatus of the plurality of information processing apparatuses via a communication unit of the second apparatus. The communication unit of a first apparatus of the plurality of information processing apparatuses executes at least one of a process of storing redundant data which is generated by making redundant data stored in the storage unit of the first apparatus in the storage unit of the second apparatus via the communication unit of the second apparatus, and a process of acquiring redundant data which is generated by making redundant data stored in the storage unit of the second apparatus via the communication unit of the second apparatus, and storing the acquired data in the storage unit of the first apparatus.

公开(公告)号：US09703621B2

公开(公告)日：2017-07-11

申请号：US14796790

申请日：2015-07-10

Applicant: FUJITSU LIMITED

Inventor： Masahiko Yamada ,  Tsuyoshi Hashimoto

IPC: G11C29/00 ,  G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0709

Abstract: An information processing apparatus, includes a processor, and memory storing instructions for causing the processor to allocate a node in an information processing system including the information processing apparatus as an investigation node configured to perform an investigation of data stored in memory of a node of which an error is detected. The processor further instructs the investigation node to acquire data to be investigated from the node of which the error is detected, instructs the investigation node to perform an operation for determining whether a predetermined value in the acquired data is a normal value, and determines that a failure occurs in the node of which the error is detected when the predetermined value is not a normal value.

公开(公告)号：US09558038B2

公开(公告)日：2017-01-31

申请号：US14704316

申请日：2015-05-05

Applicant: FUJITSU LIMITED

Inventor： Yuta Higuchi ,  Mio Nakagawa ,  Tsuyoshi Hashimoto

IPC: G06F9/46 ,  G06F15/173 ,  H04B1/66 ,  G06F9/50

CPC classification number: G06F9/5005 ,  G06F11/08 ,  G06F11/18 ,  G06F11/20 ,  G06F11/2033 ,  G06F11/2051

Abstract: A system to which the present invention has been applied includes a plurality of information processing apparatuses connected to each other and a management device that divides a first number of pieces of management data needed for management of the plurality of information processing apparatuses into a second number of pieces of management data, the second number being equal to or greater than the first number, and that transmits the second number of pieces of management data obtained by the division respectively to the plurality of information processing apparatuses.

Abstract translation: 已经应用了本发明的系统包括彼此连接的多个信息处理设备和将多个信息处理设备管理所需的第一数量的管理数据划分为第二数量的管理设备 管理数据，第二数量等于或大于第一数量，并且将通过分割获得的第二数量的管理数据分别发送到多个信息处理设备。

公开(公告)号：US10594591B2

公开(公告)日：2020-03-17

申请号：US16033258

申请日：2018-07-12

Applicant: FUJITSU LIMITED

Inventor： Akio Houjyo ,  Tsuyoshi Hashimoto

IPC: H04L12/28 ,  H04L12/751 ,  H04B7/14 ,  H04W40/24

Abstract: An information processing apparatus is configured to receive a request for communication between a first node and a second node included in a parallel calculation system, acquire job execution information relating a job to be executed by the parallel calculation system, generate connected graph information based on first information on the first node, second information on the second node, the job execution information, and topology information indicating a topology of the plurality of nodes, generate, based on the connected graph information, route information indicating a plurality of routes used when the communication between the first node and the second node is executed, specify, based on the route information, a route having the lowest passing cost among the plurality of routes; and specify a node included in the specified route as a relay node based on positions of the plurality of nodes in the specified route.