公开(公告)号：US20150301557A1

公开(公告)日：2015-10-22

申请号：US14256810

申请日：2014-04-18

申请人： FUJITSU LIMITED

发明人： William W. WALKER ,  Pradip THACHILE ,  Nikola NEDOVIC

IPC分类号： G06F1/10 ,  H04L7/033 ,  H04B1/40 ,  H03L7/08

CPC分类号： G06F1/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/22 ,  H03L2207/06 ,  H04L7/0331

摘要： A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

摘要翻译： 时钟倍增和分配系统包括第一锁相环电路，第二锁相环电路和电耦合第一锁相环电路和第二锁相环电路的时钟分配网络 。 第一锁相环电路可以包括第一反馈回路，其包括第一整数分频器电路，并且可以被配置为使用参考时钟产生第一时钟。 第一时钟的频率可以大于参考时钟的频率。 第二锁相环电路可以包括第二反馈回路，其包括第二整数分频器电路，并且可以被配置为使用第一时钟产生第二时钟。 第二时钟的频率可以大于第一时钟的频率。

公开(公告)号：US20150356227A1

公开(公告)日：2015-12-10

申请号：US14296264

申请日：2014-06-04

申请人： FUJITSU LIMITED

发明人： William W. WALKER

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/504 ,  G06F17/5077

摘要： A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data.

摘要翻译： 一种方法可以包括获得描述门级电路设计的门级电路设计数据。 门级电路设计数据可以包括每个多个单元的一个或多个实例，每个单元可以与相应的默认单元静态定时数据和相应的默认单元应力数据相关联。 该方法可以包括选择多个小区之一的实例之一，确定与所选实例相关联的设计中压力数据，以及确定设计中压力数据是否不在默认小区应力数据的容限内。 响应于设计中的压力数据不在默认单元应力数据的容限内，该方法可以包括生成描述所选实例的定时性能的设计中的静态定时数据，并且将门级电路设计数据如 所选择的实例与设计中的静态时序数据相关联。

公开(公告)号：US20150229316A1

公开(公告)日：2015-08-13

申请号：US14179600

申请日：2014-02-13

申请人： FUJITSU LIMITED

发明人： William W. WALKER ,  Nikola NEDOVIC

IPC分类号： H03L7/099

CPC分类号： H03L7/099 ,  H03B1/00 ,  H03B19/12 ,  H03B27/00 ,  H03K3/0315 ,  H03L7/0805 ,  H03L7/24

摘要： A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.

摘要翻译： 用于信号产生的系统可以包括包括第一振荡器的锁相环。 系统还可以包括第二振荡器。 第一振荡器可以被配置为基于由锁相环产生的锁相环控制信号来产生第一信号。 第二振荡器可以被配置为基于锁相环控制信号产生第二信号，使得第一信号的自由运行频率近似等于第二信号的自由运行频率，以获得第二信号之间的注入锁定 当来自第一振荡器的能量耦合到第二振荡器中时，第一振荡器和第二振荡器。

公开(公告)号：US20150222254A1

公开(公告)日：2015-08-06

申请号：US14172758

申请日：2014-02-04

申请人： FUJITSU LIMITED

发明人： William W. WALKER

IPC分类号： H03K5/05 ,  H03K21/00

CPC分类号： H03K5/05 ,  G01R15/16 ,  G01R27/02 ,  G01R27/2605 ,  H03K3/017 ,  H03K5/1565 ,  H03K7/08 ,  H03K19/0016 ,  H03K21/00 ,  H03K21/08

摘要： A digital duty-cycle correction circuit may include an adjustment unit that may be configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal and a sampling unit that may be configured to sample the adjusted oscillating signal. The circuit may also include a counting unit that may be configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low and high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusting oscillating signal. The circuit may also include a comparing and filtering unit that may be configured to generate the adjust signal based on a comparison of the indication with a comparison count. The indication may be adjustable such that the oscillating signal's duty cycle is adjustable.

摘要翻译： 数字占空比校正电路可以包括调整单元，其可以被配置为基于调整信号调整振荡信号的占空比以产生调整的振荡信号，以及可以被配置为对经调整的振荡信号进行采样的采样单元 。 电路还可以包括计数单元，其可以被配置为生成处于低电平和高电平的经调整的振荡信号的采样数量的指示，并且使用可选择的占空比修改信号基于期望的 调整振荡信号的占空比。 电路还可以包括比较和滤波单元，其可以被配置为基于指示与比较计数的比较来生成调整信号。 该指示可以是可调节的，使得振荡信号的占空比是可调节的。