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1.发明申请Digital architecture for reconfigurable computing in digital signal processing 有权用于数字信号处理中的可重构计算的数字架构公开(公告)号：US20050015573A1
公开(公告)日：2005-01-20
申请号：US10770122
申请日：2004-02-02
申请人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
发明人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
CPC分类号： G06F9/3885 , G06F9/3877 , G06F9/3897 , G06F15/7867
摘要： A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.
摘要翻译： 数字嵌入式架构包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，并且包括：处理器，被构造为通过通用硬连线计算逻辑实现非常长的指令字精炼模式，以及额外的数据描述 信道包括基于由专用控制单元控制的基于可配置查找表的基于流水线阵列的可重配置功能单元，从而缓解了关键内核算法的详细描述。
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2.发明授权Digital architecture for reconfigurable computing in digital signal processing 有权用于数字信号处理中的可重构计算的数字架构公开(公告)号：US07225319B2
公开(公告)日：2007-05-29
申请号：US10770122
申请日：2004-02-02
申请人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
发明人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
CPC分类号： G06F9/3885 , G06F9/3877 , G06F9/3897 , G06F15/7867
摘要： A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.
摘要翻译： 数字嵌入式架构包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，并且包括：处理器，被构造为通过通用硬连线计算逻辑实现非常长的指令字精炼模式，以及额外的数据描述 信道包括基于由专用控制单元控制的基于可配置查找表的基于流水线阵列的可重配置功能单元，从而缓解了关键内核算法的详细描述。
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公开(公告)号：US07193437B2
公开(公告)日：2007-03-20
申请号：US10778913
申请日：2004-02-13
申请人： Andrea Cappelli , Luca Ciccarelli , Andrea Lodi , Mario Toma , Fabio Campi
发明人： Andrea Cappelli , Luca Ciccarelli , Andrea Lodi , Mario Toma , Fabio Campi
IPC分类号： H03K19/177 , H01L25/00 , G11C11/00 , G11C7/10
CPC分类号： H03K19/1776 , H01L27/11803 , H03K19/17736
摘要： An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.
摘要翻译： 一种优化的架构，用于在可重构门阵列中实现逻辑块和路由线之间的连接，包括通过连接线连接不同逻辑元件的输入和输出的连接块，每个连接块包括一行传输晶体管开关; 以及用于驱动传输晶体管开关的解码级。
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4.发明授权Switch block and corresponding switch matrix, in particular for FPGA architectures 有权开关块和相应的开关矩阵，特别适用于FPGA架构公开(公告)号：US07463055B2
公开(公告)日：2008-12-09
申请号：US11215301
申请日：2005-08-30
申请人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
发明人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC分类号： H03K19/173
CPC分类号： H03K19/17736
摘要： A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
摘要翻译： 适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。 切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。
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5.发明申请Switch block and corresponding switch matrix, in particular for FPGA architectures 有权开关块和相应的开关矩阵，特别适用于FPGA架构公开(公告)号：US20060103420A1
公开(公告)日：2006-05-18
申请号：US11215301
申请日：2005-08-30
申请人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
发明人： Luca Ciccarelli , Carlo Chiesa , Andrea Lodi , Roberto Giansante , Mario Toma , Fabio Campi
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
摘要翻译： 适于实现连接到其上的互连线之间的连接的开关块，所述互连线至少包括连接到互连线的开关块，并且至少包括缓冲级，并且依次连接到多个晶体管。 切换块包括插入在多个SRAM单元与切换块的多个晶体管的各控制端之间的解码级。
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6.发明授权公开(公告)号：US08910103B2
公开(公告)日：2014-12-09
申请号：US12648099
申请日：2009-12-28
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
摘要翻译： 一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。 该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。 因此获得部分预先布置的计算逻辑。
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7.发明申请METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC INTEGRATED CIRCUIT) ACCELERATOR 有权设计高性能ASIC（应用特定集成电路）加速器的方法公开(公告)号：US20100169857A1
公开(公告)日：2010-07-01
申请号：US12648099
申请日：2009-12-28
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
摘要翻译： 一种用于设计用于数字信号处理的加速器的方法，包括通过用固定拓扑预先布置DSP加速器的控制逻辑来定义可完全预编程的软件，以获得完全预先布置的控制逻辑。 该方法还包括通过定制可配置布局区域来定义硬件可编程部分预布置的宏，从而基于与DSP加速器的应用相关的计算内核映射计算逻辑。 因此获得部分预先布置的计算逻辑。
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