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    Silicon-germanium heterojunction bipolar transistor
    1.
    发明授权
    Silicon-germanium heterojunction bipolar transistor 有权
    硅 - 锗异质结双极晶体管

    公开(公告)号：US08378457B2

    公开(公告)日：2013-02-19

    申请号：US13239250

    申请日：2011-09-21

    申请人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    发明人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    IPC分类号： H01L27/102

    CPC分类号： H01L29/7378 ,  H01L21/26513 ,  H01L29/0821 ,  H01L29/41708

    摘要： A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

    摘要翻译： 公开了一种形成在硅衬底上的SiGe HBT。 有源区域由场氧化物区域隔离; 在有源区域中形成集电极区域并延伸到场氧化物区域的底部; 伪掩埋层形成在场氧化物区域的底部，其中每个伪掩埋层与有源区域的横向距离分离并连接到集电极区域的横向延伸部分; 第一深孔触点形成在场氧化物区域中的伪掩埋层的顶部上以拾取集电极; 在集电区域的横向延伸部分的顶部上的场氧化物区域中形成多个具有浮动结构的第二深孔触点，其中在第二深孔触点的底部形成有N型注入区域。

    SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
    2.
    发明申请
    SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 有权
    硅 - 锗绝缘双极晶体管

    公开(公告)号：US20120074465A1

    公开(公告)日：2012-03-29

    申请号：US13239250

    申请日：2011-09-21

    申请人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    发明人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    IPC分类号： H01L29/737

    CPC分类号： H01L29/7378 ,  H01L21/26513 ,  H01L29/0821 ,  H01L29/41708

    摘要： A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

    摘要翻译： 公开了一种形成在硅衬底上的SiGe HBT。 有源区域由场氧化物区域隔离; 在有源区域中形成集电极区域并延伸到场氧化物区域的底部; 伪掩埋层形成在场氧化物区域的底部，其中每个伪掩埋层与有源区域的横向距离分离并连接到集电极区域的横向延伸部分; 第一深孔触点形成在场氧化物区域中的伪掩埋层的顶部上以拾取集电极; 在集电区域的横向延伸部分的顶部的场氧化物区域中形成多个具有浮动结构的第二深孔触点，其中在第二深孔触点的底部形成有N型注入区域。

    METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
    3.
    发明申请
    METHOD FOR MANUFACTURING SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
    硅锗绝缘双极晶体管的制造方法

    公开(公告)号：US20120064688A1

    公开(公告)日：2012-03-15

    申请号：US13229570

    申请日：2011-09-09

    申请人： Fan Chen ,  Xionbing Chen ,  Zhengliang Zhou

    发明人： Fan Chen ,  Xionbing Chen ,  Zhengliang Zhou

    IPC分类号： H01L21/331

    CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7378

    摘要： A manufacturing method of a SiGe HBT is disclosed. Alter an emitter region is formed, an ion implantation is performed with a tilt angle to a base region by using an extrinsic base ion implantation process; boron ions are implanted during the extrinsic base ion implantation with an implantation dose from 1e15 to 1e16 cm−2, an implantation energy from 5 to 30 KeV, and a tilt angle from 5 to 30 degrees. The tilt angle enables the implantation of P-type impurities into the part of the intrinsic base region at the bottom of the emitter window dielectric layer as well as the extrinsic base region, so that the base region excluding the part of the intrinsic base region in contact with the emitter region is entirely doped with P-type impurities, thus reducing the base resistance and improving the frequency characteristic of a transistor without needing to reduce its size.

    摘要翻译： 公开了SiGe HBT的制造方法。 改变发射极区域，通过使用外部基极离子注入工艺，以与基极区域倾斜的角度进行离子注入; 在离子注入期间，以离子注入量为1e15〜1e16cm-2，注入能量为5〜30KeV，倾斜角为5〜30度，注入硼离子。 倾斜角使得能够将P型杂质注入发射极窗电介质层的底部的本征基区的一部分以及外部碱性区，使得除了本征基区的部分以外的基区 与发射极区域的接触完全掺杂有P型杂质，从而降低了基极电阻并提高了晶体管的频率特性，而不需要减小其尺寸。

    Manufacturing approach for collector and a buried layer of bipolar transistor
    5.
    发明授权
    Manufacturing approach for collector and a buried layer of bipolar transistor 有权
    集电极的制造方法和双极晶体管的埋层

    公开(公告)号：US08420495B2

    公开(公告)日：2013-04-16

    申请号：US12979999

    申请日：2010-12-28

    申请人： Tzuyin Chiu ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    发明人： Tzuyin Chiu ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    IPC分类号： H01L21/338 ,  H01L21/428 ,  H01L21/38 ,  H01L21/00

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/66272

    摘要： This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

    摘要翻译： 本发明公开了双极晶体管的集电极和掩埋层的制造方法。 本发明的一个方面是通过离子注入和热退火制造伪掩埋层，即集电极掩埋层。 该伪掩埋层具有小的面积，这使得深沟槽隔离以在随后的工艺中不需要划分伪掩埋层。 另一方面是，通过离子注入形成掺杂区域，即集电极，而不是高成本的外延工艺。 本发明简化了制造过程，结果节省了制造成本。

    Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor
    7.
    发明申请
    Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor 有权
    双极晶体管集电极和N型埋层的新型制造方法

    公开(公告)号：US20110159672A1

    公开(公告)日：2011-06-30

    申请号：US12979999

    申请日：2010-12-28

    申请人： Tzuyin CHIU ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    发明人： Tzuyin CHIU ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    IPC分类号： H01L21/265

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/66272

    摘要： This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

    摘要翻译： 本发明公开了双极晶体管的集电极和掩埋层的制造方法。 本发明的一个方面是通过离子注入和热退火制造伪掩埋层，即集电极掩埋层。 该伪掩埋层具有小的面积，这使得深沟槽隔离以在随后的工艺中不需要划分伪掩埋层。 另一方面是，通过离子注入形成掺杂区域，即集电极，而不是高成本的外延工艺。 本发明简化了制造过程，结果节省了制造成本。

    PN-junction varactor in a BiCMOS process and manufacturing method of the same
    10.
    发明授权
    PN-junction varactor in a BiCMOS process and manufacturing method of the same 有权
    PN结变容二极管在BiCMOS工艺及其制造方法相同

    公开(公告)号：US08502349B2

    公开(公告)日：2013-08-06

    申请号：US13315116

    申请日：2011-12-08

    申请人： Fan Chen ,  Xiongbin Chen

    发明人： Fan Chen ,  Xiongbin Chen

    IPC分类号： H01L29/93

    CPC分类号： H01L29/93 ,  H01L27/0635 ,  H01L27/0808 ,  H01L29/66174

    摘要： A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed.

    摘要翻译： 公开了一种BiCMOS工艺中的PN结变容二极管，其包括N型区域，P型区域和N型伪掩埋层。 N型和P型区均形成有源区并相互接触，形成PN结; P型区域位于N型区域的顶部。 N型伪埋层形成在有源区两侧的浅沟槽场氧化物区域的底部，并与N型区域接触; 在浅沟槽场氧化物区域中的N型伪埋层的顶部上形成深孔接触以拾取N型区域。 还公开了BiCMOS工艺中的PN结变容二极管的制造方法。