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    Silicon-germanium heterojunction bipolar transistor
    1.
    发明授权
    Silicon-germanium heterojunction bipolar transistor 有权
    硅 - 锗异质结双极晶体管

    公开(公告)号：US08378457B2

    公开(公告)日：2013-02-19

    申请号：US13239250

    申请日：2011-09-21

    申请人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    发明人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    IPC分类号： H01L27/102

    CPC分类号： H01L29/7378 ,  H01L21/26513 ,  H01L29/0821 ,  H01L29/41708

    摘要： A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

    摘要翻译： 公开了一种形成在硅衬底上的SiGe HBT。 有源区域由场氧化物区域隔离; 在有源区域中形成集电极区域并延伸到场氧化物区域的底部; 伪掩埋层形成在场氧化物区域的底部，其中每个伪掩埋层与有源区域的横向距离分离并连接到集电极区域的横向延伸部分; 第一深孔触点形成在场氧化物区域中的伪掩埋层的顶部上以拾取集电极; 在集电区域的横向延伸部分的顶部上的场氧化物区域中形成多个具有浮动结构的第二深孔触点，其中在第二深孔触点的底部形成有N型注入区域。

    SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
    2.
    发明申请
    SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 有权
    硅 - 锗绝缘双极晶体管

    公开(公告)号：US20120074465A1

    公开(公告)日：2012-03-29

    申请号：US13239250

    申请日：2011-09-21

    申请人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    发明人： Fan Chen ,  Xiongbin Chen ,  Wensheng Qian ,  Zhengliang Zhou

    IPC分类号： H01L29/737

    CPC分类号： H01L29/7378 ,  H01L21/26513 ,  H01L29/0821 ,  H01L29/41708

    摘要： A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

    摘要翻译： 公开了一种形成在硅衬底上的SiGe HBT。 有源区域由场氧化物区域隔离; 在有源区域中形成集电极区域并延伸到场氧化物区域的底部; 伪掩埋层形成在场氧化物区域的底部，其中每个伪掩埋层与有源区域的横向距离分离并连接到集电极区域的横向延伸部分; 第一深孔触点形成在场氧化物区域中的伪掩埋层的顶部上以拾取集电极; 在集电区域的横向延伸部分的顶部的场氧化物区域中形成多个具有浮动结构的第二深孔触点，其中在第二深孔触点的底部形成有N型注入区域。

    Manufacturing approach for collector and a buried layer of bipolar transistor
    5.
    发明授权
    Manufacturing approach for collector and a buried layer of bipolar transistor 有权
    集电极的制造方法和双极晶体管的埋层

    公开(公告)号：US08420495B2

    公开(公告)日：2013-04-16

    申请号：US12979999

    申请日：2010-12-28

    申请人： Tzuyin Chiu ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    发明人： Tzuyin Chiu ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    IPC分类号： H01L21/338 ,  H01L21/428 ,  H01L21/38 ,  H01L21/00

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/66272

    摘要： This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

    摘要翻译： 本发明公开了双极晶体管的集电极和掩埋层的制造方法。 本发明的一个方面是通过离子注入和热退火制造伪掩埋层，即集电极掩埋层。 该伪掩埋层具有小的面积，这使得深沟槽隔离以在随后的工艺中不需要划分伪掩埋层。 另一方面是，通过离子注入形成掺杂区域，即集电极，而不是高成本的外延工艺。 本发明简化了制造过程，结果节省了制造成本。

    Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor
    8.
    发明申请
    Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor 有权
    双极晶体管集电极和N型埋层的新型制造方法

    公开(公告)号：US20110159672A1

    公开(公告)日：2011-06-30

    申请号：US12979999

    申请日：2010-12-28

    申请人： Tzuyin CHIU ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    发明人： Tzuyin CHIU ,  TungYuan Chu ,  YungChieh Fan ,  Wensheng Qian ,  Fan Chen ,  Jiong Xu ,  Haifang Zhang

    IPC分类号： H01L21/265

    CPC分类号： H01L29/732 ,  H01L29/0821 ,  H01L29/66272

    摘要： This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

    摘要翻译： 本发明公开了双极晶体管的集电极和掩埋层的制造方法。 本发明的一个方面是通过离子注入和热退火制造伪掩埋层，即集电极掩埋层。 该伪掩埋层具有小的面积，这使得深沟槽隔离以在随后的工艺中不需要划分伪掩埋层。 另一方面是，通过离子注入形成掺杂区域，即集电极，而不是高成本的外延工艺。 本发明简化了制造过程，结果节省了制造成本。

    SiGe HBT and method of manufacturing the same
    9.
    发明授权
    SiGe HBT and method of manufacturing the same 有权
    SiGe HBT及其制造方法

    公开(公告)号：US09012279B2

    公开(公告)日：2015-04-21

    申请号：US13613236

    申请日：2012-09-13

    申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

    发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

    IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

    摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

    摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。

    Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor
    10.
    发明授权
    Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor 有权
    伪埋层及其制造方法相同，深孔接触和双极晶体管

    公开(公告)号：US08592870B2

    公开(公告)日：2013-11-26

    申请号：US13227387

    申请日：2011-09-07

    申请人： Donghua Liu ,  Wensheng Qian

    发明人： Donghua Liu ,  Wensheng Qian

    IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288

    CPC分类号： H01L29/0821 ,  H01L21/28525 ,  H01L21/7684 ,  H01L29/0657 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7378

    摘要： The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

    摘要翻译： 本发明公开了一种伪埋层，深孔接触和双极晶体管，并且还公开了一种伪掩埋层的制造方法，包括：蚀刻硅衬底以形成有源区和浅沟; 顺序地将磷离子和砷离子注入浅沟槽的底部以形成磷杂质区和砷杂质区; 对磷杂质区域和砷杂质区域进行热退火。 采用具有快速热扩散的磷和具有缓慢热扩散的砷的伪掩埋层的注入可以改善伪埋层表面的杂质浓度，降低伪掩埋层的薄层电阻，形成良好的欧姆接触 在伪埋层和深孔之间，减小接触电阻，提高三极管器件的频率特性和电流输出。