公开(公告)号：US06593779B2

公开(公告)日：2003-07-15

申请号：US10238214

申请日：2002-09-09

申请人： Farshid Shokouhi ,  Ben Y. Sheen ,  Qi Lin

发明人： Farshid Shokouhi ,  Ben Y. Sheen ,  Qi Lin

IPC分类号： H03K522

CPC分类号： G11C16/30 ,  G01R19/0084 ,  G11C5/145

摘要： The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage. This output signal triggers the pumping of the positive charge pump. By changing the resistance within the resistor chain, the positive charge pumping may be initiated at varying negative voltages. In the present invention, additional resistance is added to or removed from the resistor chain via metal options or switches.

公开(公告)号：US06249458B1

公开(公告)日：2001-06-19

申请号：US09603462

申请日：2000-06-22

申请人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

发明人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

IPC分类号： G11C1600

CPC分类号： G11C16/12 ,  G11C16/30

摘要： A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.

摘要翻译： 一种浮动栅极存储器件，其包括用于选择性地将两个或更多个负电压传送到公共节点（例如，驱动电路的负极）的开关电路。 开关电路包括分别连接在两个负电压和公共节点之间的两个开关。 每个开关包括串联连接的三阱NMOS晶体管，其在公共节点之间提供负电压源之间的双重隔离结构。 在每个开关中的串联连接的三阱NMOS晶体管之间提供可选的三重P阱电阻器，其包括由系统电压源（例如VCC）偏置的深N阱区域，以反向偏置中心P- 井区。

公开(公告)号：US06272060B1

公开(公告)日：2001-08-07

申请号：US09569820

申请日：2000-05-12

申请人： Ben Y. Sheen ,  Michael G. Ahrens

发明人： Ben Y. Sheen ,  Michael G. Ahrens

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C19/00

摘要： A shift register system is disclosed wherein shift registers buffering memory data perform shift operations in response to a set of sub-clock signals. The set of sub-clock signals comprise nested sub-clock signals having non-overlapping transitions formed from a system clock signal or power on reset signal. Each shift register (or bank of shift registers) responds to a different sub-clock signal. As a result, shift operations are spread out over a period of time rather than occurring simultaneously. Thus, the current drawn during each shift operation is similarly spread out over a period of time. The maximum current drawn during any one shift operation is inversely proportional to the number of non-overlapping sub-clock signal. Therefore, the maximum current drawn (i.e., current spike) drawn during memory operations is minimized.

摘要翻译： 公开了一种移位寄存器系统，其中缓冲存储器数据的移位寄存器响应于一组子时钟信号执行移位操作。 子组件子信号包括具有由系统时钟信号或上电复位信号形成的非重叠跳变的嵌套子时钟信号。 每个移位寄存器（或移位寄存器组）响应不同的子时钟信号。 因此，班次操作在一段时间内分散，而不是同时发生。 因此，在每个换档操作期间画出的电流在一段时间内相似地展开。 在任何一个移位操作期间拉出的最大电流与非重叠子时钟信号的数量成反比。 因此，在存储器操作期间画出的最大电流（即，电流尖峰）被最小化。

公开(公告)号：US5572474A

公开(公告)日：1996-11-05

申请号：US503807

申请日：1995-07-18

申请人： Ben Y. Sheen ,  Timothy M. Lacey ,  Sammy Cheung

发明人： Ben Y. Sheen ,  Timothy M. Lacey ,  Sammy Cheung

IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C13/00

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/14

摘要： A pseudo-differential sense amplifier for sensing the state of an array memory cell by reference to a reference cell in a predetermined state. The sense amplifier has an input stage coupled to the array memory cell, which provides signals to a differential stage from which an output is generated. The input stage has reference and array side cascode circuits in which the components are matched on each side so as to eliminate process, temperature, and other extraneous variations from influencing the differential output. An enabling signal to the array side of the input stage is delayed with respect to the reference side such that voltage fluctuations externally introduced into the signals passed from the input stage to the differential stage do not cause erroneous switching and/or glitches to appear at the sense amplifier output. Additionally, parallel cascode and load transistors can be selectively switched into the input stage circuit to enable selectable cascode transconductance and circuit loading to effect selectable speed and/or input stage voltage swing.

摘要翻译： 一种伪差分读出放大器，用于通过参考预定状态的参考单元来感测阵列存储单元的状态。 读出放大器具有耦合到阵列存储单元的输入级，其向产生输出的差分级提供信号。 输入级具有参考和阵列侧共源共栅电路，其中组件在每一侧匹配，以消除过程，温度和其他外来变化影响差分输出。 输入级的阵列侧的使能信号相对于参考侧被延迟，使得外部引入到从输入级传递到差分级的信号中的电压波动不会引起错误的切换和/或毛刺出现在 感测放大器输出。 此外，可以将并联共源共栅和负载晶体管选择性地切换到输入级电路，以实现可选择的共源共栅跨导和电路负载来实现可选择的速度和/或输入级电压摆幅。