公开(公告)号：US20130092981A1

公开(公告)日：2013-04-18

申请号：US13613151

申请日：2012-09-13

申请人： Feng Han ,  Donghua Liu ,  Jun Hu ,  Wenting Duan ,  Jing Shi

发明人： Feng Han ,  Donghua Liu ,  Jun Hu ,  Wenting Duan ,  Jing Shi

IPC分类号： H01L29/737

CPC分类号： H01L29/0817 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.

摘要翻译： 公开了具有位置控制的发射极 - 基极结的SiGe HBT。 SiGe HBT包括：由N掺杂的有源区形成的集电极区域; 基底区域，形成在集电极区域上并且包括基底外延层，所述基底外延层包括SiGe层和形成在其上的覆盖层，所述SiGe层由掺杂有P型杂质的SiGe外延层形成，所述封盖 层掺杂有N型杂质; 以及形成在所述基极区上的发射极区域，所述发射极区域由多晶硅形成。 通过优化掺杂在基极区域中的杂质的分布，可以实现发射极 - 基极结的可控位置和其反向耐压的可调节性，从而提高了工艺的稳定性并提高了晶片内的均匀性。

公开(公告)号：US09012279B2

公开(公告)日：2015-04-21

申请号：US13613236

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。

公开(公告)号：US20130113020A1

公开(公告)日：2013-05-09

申请号：US13613236

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。

公开(公告)号：US20130113078A1

公开(公告)日：2013-05-09

申请号：US13613209

申请日：2012-09-13

申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/94 ,  H01L29/66181

摘要： A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

摘要翻译： 公开了SiGe HBT工艺中的PIS电容器，其中PIS电容器包括：硅衬底; 在硅衬底中形成的P阱和浅沟槽隔离; 形成在P阱的上部的P型重掺杂区域; 在P型重掺杂区域上形成氧化物层和SiGe外延层; 在氧化物层和SiGe外延层的侧壁上形成间隔物; 以及用于拾取P阱和SiGe外延层的接触孔，并将P阱和SiGe外延层中的每一个连接到金属线。 还公开了一种制造PIS电容器的方法。 通过使用SiGe HBT工艺制造本发明的PIS电容器，从而为SiGe HBT工艺提供了一种更多的器件选择。