公开(公告)号：US07129738B2

公开(公告)日：2006-10-31

申请号：US10379006

申请日：2003-03-04

申请人： Feng Lin ,  Brian Johnson

发明人： Feng Lin ,  Brian Johnson

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous circuit that is indicative of an impedance mismatch between a driver circuit and a load. The method also includes selecting one of a plurality of impedances of the driver circuit to reduce the impedance mismatch in response to the signal.

摘要翻译： 本发明提供了一种用于校准集成电路器件中的驱动器阻抗的方法和装置。 该方法包括提供来自指示驱动器电路和负载之间的阻抗失配的来自同步电路的信号。 该方法还包括选择驱动器电路的多个阻抗中的一个以减少响应于该信号的阻抗失配。

公开(公告)号：US20060044891A1

公开(公告)日：2006-03-02

申请号：US10931472

申请日：2004-08-31

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US06930955B2

公开(公告)日：2005-08-16

申请号：US10851081

申请日：2004-05-24

申请人： Brian Johnson ,  Brent Keeth ,  Feng Lin

发明人： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/4076

摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

摘要翻译： 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US06839301B2

公开(公告)日：2005-01-04

申请号：US10425069

申请日：2003-04-28

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G11C7/22 ,  G11C29/02 ,  G11C8/00

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法和装置以及包含延迟锁定环路的系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将测试信号切换到正向延迟路径，并测量在前向延迟路径和反馈延迟路径周围的测试信号遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07812593B2

公开(公告)日：2010-10-12

申请号：US12202685

申请日：2008-09-02

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G01R17/16

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward loop path and the feedback loop path. The phase detector is coupled to both the forward and feedback loop path circuits and is configured to periodically adjust responsive to a calculated loop delay of the test clock signal. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法和包含延迟锁定环路的设备。 延迟锁定环路包括正向环路径，反馈环路径和相位检测器。 临时切换测试时钟信号以遍历正向环路径和反馈环路径。 相位检测器耦合到正向和反馈环路径电路两者，并且被配置为响应于所计算的测试时钟信号的环路延迟而周期性地调整。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07420361B2

公开(公告)日：2008-09-02

申请号：US11519556

申请日：2006-09-12

申请人： Feng Lin ,  J. Brian Johnson

发明人： Feng Lin ,  J. Brian Johnson

IPC分类号： G01R13/02

CPC分类号： G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

摘要翻译： 描述了延迟锁定环路，信号锁定方法以及包含延迟锁定环路的设备和系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将内部测试信号切换到正向延迟路径，并测量在正向延迟路径和反馈延迟路径周围的内部测试信号的遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。

公开(公告)号：US07269094B2

公开(公告)日：2007-09-11

申请号：US11352131

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060126406A1

公开(公告)日：2006-06-15

申请号：US11352142

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US06762974B1

公开(公告)日：2004-07-13

申请号：US10389807

申请日：2003-03-18

申请人： Brian Johnson ,  Brent Keeth ,  Feng Lin

发明人： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/4076

摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

摘要翻译： 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US06687185B1

公开(公告)日：2004-02-03

申请号：US10230221

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson ,  Feng Lin

发明人： Brent Keeth ,  Brian Johnson ,  Feng Lin

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C11/4076 ,  G11C2207/2281

摘要： An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.

摘要翻译： 一种用于协调从外部时钟信号导出的内部时钟信号的可变定时的装置和方法，以确保读取数据和用于锁存读取数据的读取时钟同步并以指定的读取延迟到达数据锁存器。 在延迟锁定环路电路中，从外部时钟信号产生读时钟，并且响应于读命令产生的起始信号通过与延迟锁定环相对应的延迟电路，使得读时钟信号和延迟 启动信号受到相同的内部时序变化。 延迟启动信号用于通过读时钟信号控制读数据的输出。