利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.053 秒)

    Design rule correction system and method
    1.
    发明授权
    Design rule correction system and method 失效
    设计规则校正系统及方法

    公开(公告)号：US06189132B1

    公开(公告)日：2001-02-13

    申请号：US09057961

    申请日：1998-04-09

    申请人： Fook-Luen Heng ,  Zhan Chen ,  Gustavo E. Tellez ,  John Cohn ,  Rani Narayan

    发明人： Fook-Luen Heng ,  Zhan Chen ,  Gustavo E. Tellez ,  John Cohn ,  Rani Narayan

    IPC分类号： G06F1750

    CPC分类号： G06F17/5081

    摘要： A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.

    摘要翻译： 呈现了根据多个预定标准修改多个对象的布局的方法。 定义了一个目标函数，用于测量布局中对象的位置扰动和分离扰动。 使用线性约束在设计规则和用于描述布局对象之间的分离的目标函数方面定义线性系统。 解决线性系统以同时消除违反设计规则的情况，并且根据线性系统的解决方案来修改布局中对象的形状和位置，使得布局中的对象的总扰动减小。 还提出了用于实现本发明的系统。

    Practical method for hierarchical-preserving layout optimization of integrated circuit layout
    2.
    发明授权
    Practical method for hierarchical-preserving layout optimization of integrated circuit layout 失效
    集成电路布局分层维护布局优化的实用方法

    公开(公告)号：US06986109B2

    公开(公告)日：2006-01-10

    申请号：US10438625

    申请日：2003-05-15

    申请人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

    发明人： Robert J. Allen ,  Fook-Luen Heng ,  Alexey Y. Lvov ,  Kevin W. McCullen ,  Sriram Peri ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

    摘要翻译： 本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。 这些变量被约束为整数。 本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。 本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。 这产生了简化的布局方程和简化的目标函数。 这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。