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公开(公告)号：US20120151247A1
公开(公告)日：2012-06-14
申请号：US13159580
申请日：2011-06-14
IPC分类号： G06F11/20
CPC分类号： H04L45/28 , H04L1/22 , H04L1/24 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L45/22 , H04L69/40
摘要： A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
摘要翻译： 多个并行通信线路的通信链路包括至少一个冗余线路。 在第一方面，线路一次一个地重新校准，而其他线路携带功能数据。 如果检测到故障，故障线路被禁用，其余的已校准线路传输功能数据。 在第二方面，在校准期间从异常检测到即将发生的线路故障。 在第三方面，通过确定发生每个检测到的错误的逻辑通道，并且将逻辑通道映射到当前携带逻辑车道数据的物理线路，从接收器电路输出检测线路故障。
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公开(公告)号：US08767531B2
公开(公告)日：2014-07-01
申请号：US13159580
申请日：2011-06-14
CPC分类号： H04L45/28 , H04L1/22 , H04L1/24 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L45/22 , H04L69/40
摘要： A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
摘要翻译： 多个并行通信线路的通信链路包括至少一个冗余线路。 在第一方面，线路一次一个地重新校准，而其他线路携带功能数据。 如果检测到故障，故障线路被禁用，其余的已校准线路传输功能数据。 在第二方面，在校准期间从异常检测到即将发生的线路故障。 在第三方面，通过确定发生每个检测到的错误的逻辑通道，并且将逻辑通道映射到当前携带逻辑车道数据的物理线路，从接收器电路输出检测线路故障。
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3.发明申请Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines 审中-公开使用冗余线路协调数据通信设备中的通信接口活动公开(公告)号：US20120106539A1
公开(公告)日：2012-05-03
申请号：US12913064
申请日：2010-10-27
IPC分类号： H04L12/28
CPC分类号： H04J3/06 , G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A parallel data link includes a redundant line. The redundant line permits one line to be calibrated while the others carry functional data, a switching mechanism enabling each line to be selected in turn for calibration. Control information for controlling the link, which is preferably for coordinating calibration activity, is communicated on the line selected for calibration. Preferably, the link is bi-directional, having a separate redundant line in each direction, enabling a bi-directional handshaking protocol to be used for communicating control information. Preferably, the lines selected for calibration are time-multiplexed to carry calibration patterns and control information at different time intervals.
摘要翻译： 并行数据链路包括冗余线路。 冗余线路允许一行校准，而另一条线路进行功能数据，切换机制使每条线路依次被选择进行校准。 用于控制链接的控制信息，其优选用于协调校准活动，在选择用于校准的线上传送。 优选地，链路是双向的，在每个方向上具有单独的冗余线路，使得双向握手协议能够用于传送控制信息。 优选地，选择用于校准的线被时分复用以在不同的时间间隔传送校准图案和控制信息。
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4.发明授权公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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5.发明授权Calibration of multiple parallel data communications lines for high skew conditions 失效多个并行数据通信线路的校准用于高偏斜条件公开(公告)号：US08681839B2
公开(公告)日：2014-03-25
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译： 并行数据链路包括冗余线路。 一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。 开关位于对准机构的下游，以便数据输入到开关的数据偏移。 优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。 优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。
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公开(公告)号：US20080201599A1
公开(公告)日：2008-08-21
申请号：US12048405
申请日：2008-03-14
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译： 公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。 接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。 忙接口对准模式可用于加扰和解扰操作数据。 接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。
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7.发明申请Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions 失效多个并行数据通信线路的校准用于高歪斜条件公开(公告)号：US20120106687A1
公开(公告)日：2012-05-03
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译： 并行数据链路包括冗余线路。 一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。 开关位于对准机构的下游，以便数据输入到开关的数据偏移。 优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。 优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。
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公开(公告)号：US08001412B2
公开(公告)日：2011-08-16
申请号：US12048405
申请日：2008-03-14
IPC分类号： G06F1/04
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译： 公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。 接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。 忙接口对准模式可用于加扰和解扰操作数据。 接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。
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9.发明申请公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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公开(公告)号：US07412618B2
公开(公告)日：2008-08-12
申请号：US11055817
申请日：2005-02-11
IPC分类号： G06F1/04
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译： 公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。 接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。 忙接口对准模式可用于加扰和解扰操作数据。 接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。
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