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    Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition
    1.
    发明授权
    Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition 有权
    通过在阻挡层沉积期间进行沉积/蚀刻循环，在BEOL处理期间减少半导体衬底的污染

    公开(公告)号：US08039400B2

    公开(公告)日：2011-10-18

    申请号：US12418857

    申请日：2009-04-06

    申请人： Frank Koschinsky ,  Matthias Lehr ,  Holger Schuehrer

    发明人： Frank Koschinsky ,  Matthias Lehr ,  Holger Schuehrer

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  Y02P80/30

    摘要： A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

    摘要翻译： 可以基于一个或多个沉积/蚀刻循环形成半导体器件的金属化系统的导电阻挡材料，从而在斜面区域中提供减小的材料厚度，同时增强半导体的有源区域中的总厚度均匀性 基质。 在一些说明性实施例中，可以使用两个或更多个沉积/蚀刻循环，从而提供为模具区域中的阻挡层厚度选择减小的目标值的可能性，同时在斜面区域中也获得显着减小的厚度。

    REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION
    2.
    发明申请
    REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION 有权
    在玻璃沉积过程中通过执行沉积/蚀刻循环来降低烧结过程中半导体衬底的污染

    公开(公告)号：US20090325378A1

    公开(公告)日：2009-12-31

    申请号：US12418857

    申请日：2009-04-06

    申请人： Frank Koschinsky ,  Matthias Lehr ,  Holger Schuehrer

    发明人： Frank Koschinsky ,  Matthias Lehr ,  Holger Schuehrer

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  Y02P80/30

    摘要： A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

    摘要翻译： 可以基于一个或多个沉积/蚀刻循环形成半导体器件的金属化系统的导电阻挡材料，从而在斜面区域中提供减小的材料厚度，同时增强半导体的有源区域中的总体厚度均匀性 基质。 在一些说明性实施例中，可以使用两个或更多个沉积/蚀刻循环，从而提供为模具区域中的阻挡层厚度选择减小的目标值的可能性，同时还在斜面区域中获得显着减小的厚度。

    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES
    9.
    发明申请
    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES 有权
    半导体器件非破坏性金属分层监测技术

    公开(公告)号：US20070178691A1

    公开(公告)日：2007-08-02

    申请号：US11536730

    申请日：2006-09-29

    申请人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    发明人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

    Technique for non-destructive metal delamination monitoring in semiconductor devices
    10.
    发明授权
    Technique for non-destructive metal delamination monitoring in semiconductor devices 有权
    半导体器件中非破坏性金属分层监测技术

    公开(公告)号：US07638424B2

    公开(公告)日：2009-12-29

    申请号：US11536730

    申请日：2006-09-29

    申请人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    发明人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。