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1.发明授权Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors 有权在包括紧密间隔的晶体管的半导体器件的接触电平的电介质材料中的空隙密封公开(公告)号：US08129276B2
公开(公告)日：2012-03-06
申请号：US12693545
申请日：2010-01-26
申请人： Ralf Richter , Kai Frohberg , Holger Schuehrer
发明人： Ralf Richter , Kai Frohberg , Holger Schuehrer
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L21/76897 , H01L21/823425
摘要： In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.
摘要翻译： 在复杂的半导体器件中，可以基于位于紧密间隔的晶体管元件之间的空隙形成接触结构，其中沿着空隙的不利的金属迁移可以通过在蚀刻接触开口之后并且在填充接触金属之前密封空隙来抑制 。 因此，在已建立的双重应力衬垫方法中可以避免显着的屈服损失，同时可以实现优异的装置性能。
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2.发明申请REDUCING METAL VOIDS IN A METALLIZATION LAYER STACK OF A SEMICONDUCTOR DEVICE BY PROVIDING A DIELECTRIC BARRIER LAYER 有权通过提供介电阻挡层在半导体器件的金属层堆叠中减少金属离子公开(公告)号：US20100109161A1
公开(公告)日：2010-05-06
申请号：US12565323
申请日：2009-09-23
申请人： Holger Schuehrer , Juergen Boemmels
发明人： Holger Schuehrer , Juergen Boemmels
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76832 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as isolated copper voids and the like may be reduced without significantly affecting overall performance of the metallization system.
摘要翻译： 基于铜和低k电介质材料的金属化系统可以通过在低k介电材料的图案化之后提供增强的表面条件的附加电介质材料来有效地形成。 因此，可以降低诸如隔离铜空隙等的缺陷，而不会显着影响金属化系统的整体性能。
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公开(公告)号：US20100102435A1
公开(公告)日：2010-04-29
申请号：US12259357
申请日：2008-10-28
申请人： E. Todd RYAN , Holger SCHUEHRER , Seung-Hyun RHEE
发明人： E. Todd RYAN , Holger SCHUEHRER , Seung-Hyun RHEE
CPC分类号： H01L23/562 , H01L23/3121 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.
摘要翻译： 提供具有降低的拉伸应力的半导体封装。 半导体封装包括封装衬底和半导体管芯。 半导体管芯电耦合和物理耦合到封装衬底并且包括并入其中的应力消除层。 应力消除层在半导体管芯内具有预定的结构和预定位置，用于在半导体封装的加热和冷却期间减小半导体封装的拉伸应力。
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4.发明申请TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES 有权半导体器件非破坏性金属分层监测技术公开(公告)号：US20070178691A1
公开(公告)日：2007-08-02
申请号：US11536730
申请日：2006-09-29
申请人： Ralf Richter , Carsten Peters , Holger Schuehrer
发明人： Ralf Richter , Carsten Peters , Holger Schuehrer
IPC分类号： H01L21/4763
CPC分类号： H01L23/544 , H01L21/7684 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.
摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。
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5.发明申请METHOD FOR REMOVING A PASSIVATION LAYER PRIOR TO DEPOSITING A BARRIER LAYER IN A COPPER METALLIZATION LAYER 有权在铜箔金属化层中沉积障碍层之前移除钝化层的方法公开(公告)号：US20070123034A1
公开(公告)日：2007-05-31
申请号：US11468834
申请日：2006-08-31
申请人： Holger Schuehrer , Tobias Letz , Frank Koschinsky
发明人： Holger Schuehrer , Tobias Letz , Frank Koschinsky
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/02071 , H01L21/76814 , H01L21/76843
摘要： By forming a thin passivation layer after the formation of openings connecting to a highly reactive metal region, any queue time effects may be significantly reduced. Prior to the deposition of a barrier/adhesion layer, the passivation layer may be efficiently removed on the basis of a heat treatment so as to initiate material removal by evaporation.
摘要翻译： 通过在形成连接到高反应性金属区域的开口形成薄钝化层之后，可以显着地减少任何排队时间效应。 在沉积阻挡层/粘合层之前，可以在热处理的基础上有效地去除钝化层，以便通过蒸发引发材料去除。
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6.发明申请CONTACT OPTIMIZATION FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS 有权联系优化用于增强闭环间隔晶体管中的应力传递公开(公告)号：US20100327367A1
公开(公告)日：2010-12-30
申请号：US12823438
申请日：2010-06-25
申请人： Ralf Richter , Kai Frohberg , Holger Schuehrer
发明人： Ralf Richter , Kai Frohberg , Holger Schuehrer
IPC分类号： H01L27/092
CPC分类号： H01L23/485 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L21/84 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By appropriately designing the geometric configuration of a contact level of a sophisticated semiconductor device, the tensile stress level of contact elements in N-channel transistors may be increased, while the tensile strain component of contact elements caused in the P-channel transistor may be reduced.
摘要翻译： 通过适当地设计复杂半导体器件的接触电平的几何形状，可以增加N沟道晶体管中的接触元件的拉伸应力水平，同时在P沟道晶体管中引起的接触元件的拉伸应变分量可能减小 。
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7.发明授权公开(公告)号：US07820536B2
公开(公告)日：2010-10-26
申请号：US11468834
申请日：2006-08-31
申请人： Holger Schuehrer , Tobias Letz , Frank Koschinsky
发明人： Holger Schuehrer , Tobias Letz , Frank Koschinsky
IPC分类号： H01L21/20
CPC分类号： H01L21/76829 , H01L21/02071 , H01L21/76814 , H01L21/76843
摘要： By forming a thin passivation layer after the formation of openings connecting to a highly reactive metal region, any queue time effects may be significantly reduced. Prior to the deposition of a barrier/adhesion layer, the passivation layer may be efficiently removed on the basis of a heat treatment so as to initiate material removal by evaporation.
摘要翻译： 通过在形成连接到高反应性金属区域的开口形成薄钝化层之后，可以显着地减少任何排队时间效应。 在沉积阻挡层/粘合层之前，可以在热处理的基础上有效地去除钝化层，以便通过蒸发引发材料去除。
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8.发明授权Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction 有权通过X射线衍射确定SOI晶体管中的半导体合金的特性的测试结构公开(公告)号：US07763476B2
公开(公告)日：2010-07-27
申请号：US11672146
申请日：2007-02-07
申请人： Kai Frohberg , Thomas Werner , Holger Schuehrer
发明人： Kai Frohberg , Thomas Werner , Holger Schuehrer
CPC分类号： H01L22/34 , H01L27/1203
摘要： By providing test features of increased thickness in a test structure for performing an x-ray diffraction measurement for evaluating the crystalline characteristics, such as the contents of germanium, an increased accuracy may be achieved, since the patterned SOI layer may be used as an efficient reference for the required data analysis.
摘要翻译： 通过在测试结构中提供增加厚度的测试特征来执行用于评估晶体特性（例如锗含量）的X射线衍射测量，可以实现增加的精度，因为图案化SOI层可以被用作高效 参考所需的数据分析。
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9.发明申请公开(公告)号：US20080132072A1
公开(公告)日：2008-06-05
申请号：US11757575
申请日：2007-06-04
申请人： Tobias Letz , Holger Schuehrer , Markus Nopper
发明人： Tobias Letz , Holger Schuehrer , Markus Nopper
IPC分类号： H01L21/311 , B32B9/04
CPC分类号： H01L23/296 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： By forming a protection layer on the back side of a substrate prior to any process sequences, which may deposit material or material residues on the back side, the respective back side uniformity may be significantly enhanced, thereby also increasing process efficiency of subsequent back side critical processes, such as lithography, back end of line processes and the like. In one illustrative embodiment, silicon carbide may be used as a material for forming a respective protection layer.
摘要翻译： 通过在任何可能在背面沉积材料或材料残留物的工艺序列之前在衬底的背面形成保护层，可以显着增强各自的背面均匀性，从而也提高随后的背面临界的工艺效率 工艺，例如平版印刷，线后处理等。 在一个说明性实施例中，碳化硅可用作形成相应保护层的材料。
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10.发明申请公开(公告)号：US20060141775A1
公开(公告)日：2006-06-29
申请号：US11196883
申请日：2005-08-04
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/76807 , H01L21/02063
摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a material formed on a first surface of the substrate. At least one recess is formed in the layer of material. The formation of the at least one recess comprises performing a dry etching process. A contamination layer formed in the dry etching process is removed from a second surface of the substrate. Thus, contaminations of tools used in later stages of the manufacturing process resulting from flakes splitting off the contamination layer may be avoided.
摘要翻译： 形成半导体结构的方法包括提供包括形成在基板的第一表面上的材料层的基板。 在材料层中形成至少一个凹部。 至少一个凹部的形成包括进行干蚀刻工艺。 在干蚀刻工艺中形成的污染层从衬底的第二表面去除。 因此，可以避免在由污染层分离的薄片产生的制造过程的后期阶段使用的工具的污染。
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