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    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES
    1.
    发明申请
    TECHNIQUE FOR NON-DESTRUCTIVE METAL DELAMINATION MONITORING IN SEMICONDUCTOR DEVICES 有权
    半导体器件非破坏性金属分层监测技术

    公开(公告)号：US20070178691A1

    公开(公告)日：2007-08-02

    申请号：US11536730

    申请日：2006-09-29

    申请人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    发明人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

    Technique for non-destructive metal delamination monitoring in semiconductor devices
    2.
    发明授权
    Technique for non-destructive metal delamination monitoring in semiconductor devices 有权
    半导体器件中非破坏性金属分层监测技术

    公开(公告)号：US07638424B2

    公开(公告)日：2009-12-29

    申请号：US11536730

    申请日：2006-09-29

    申请人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    发明人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

    Method of reducing contamination by providing an etch stop layer at the substrate edge
    5.
    发明授权
    Method of reducing contamination by providing an etch stop layer at the substrate edge 有权
    通过在衬底边缘处提供蚀刻停止层来减少污染的方法

    公开(公告)号：US08426312B2

    公开(公告)日：2013-04-23

    申请号：US11531793

    申请日：2006-09-14

    申请人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    发明人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    IPC分类号： H01L21/461

    CPC分类号： H01L21/02087 ,  H01L21/6708 ,  H01L21/76801 ,  H01L21/76877

    摘要： By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. The etch stop layer may be formed at an early manufacturing stage so that a bevel etch process may be performed at any desired stage of the formation of circuit elements.

    摘要翻译： 通过在斜面上选择性地设置蚀刻停止层，可以在形成金属化层之前或期间执行至少一个附加的湿化学斜面蚀刻工艺，而不影响衬底材料。 因此，在形成任何阻挡层和金属层之前，电介质材料，特别是低k电介质材料可以从斜面被可靠地移除。 蚀刻停止层可以在早期制造阶段形成，从而可以在形成电路元件的任何期望阶段执行斜面蚀刻工艺。

    METHOD OF REDUCING CONTAMINATION BY PROVIDING AN ETCH STOP LAYER AT THE SUBSTRATE EDGE
    7.
    发明申请
    METHOD OF REDUCING CONTAMINATION BY PROVIDING AN ETCH STOP LAYER AT THE SUBSTRATE EDGE 有权
    通过在基板边缘处提供蚀刻停止层来减少污染的方法

    公开(公告)号：US20070155133A1

    公开(公告)日：2007-07-05

    申请号：US11531793

    申请日：2006-09-14

    申请人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    发明人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    IPC分类号： H01L21/00

    CPC分类号： H01L21/02087 ,  H01L21/6708 ,  H01L21/76801 ,  H01L21/76877

    摘要： By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. The etch stop layer may be formed at an early manufacturing stage so that a bevel etch process may be performed at any desired stage of the formation of circuit elements.

    摘要翻译： 通过在斜面上选择性地设置蚀刻停止层，可以在形成金属化层之前或期间执行至少一个附加的湿化学斜面蚀刻工艺，而不影响衬底材料。 因此，在形成任何阻挡层和金属层之前，电介质材料，特别是低k电介质材料可以从斜面被可靠地移除。 蚀刻停止层可以在早期制造阶段形成，从而可以在形成电路元件的任何期望阶段执行斜面蚀刻工艺。

    Semiconductor devices having through-contacts and related fabrication methods
    8.
    发明授权
    Semiconductor devices having through-contacts and related fabrication methods 有权
    具有通孔和相关制造方法的半导体器件

    公开(公告)号：US08951907B2

    公开(公告)日：2015-02-10

    申请号：US12968068

    申请日：2010-12-14

    申请人： Ralf Richter ,  Jens Heinrich ,  Holger Schuehrer

    发明人： Ralf Richter ,  Jens Heinrich ,  Holger Schuehrer

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485

    CPC分类号： H01L21/76808 ,  H01L21/28512 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.

    摘要翻译： 提供了半导体器件结构和相关制造方法的装置。 一种用于制造半导体器件结构的方法包括形成覆盖在与栅极结构相邻的半导体衬底中形成的掺杂区域的介电材料层，并在该介电材料层中形成导电接触。 导电接触覆盖并电连接到掺杂区域。 该方法继续通过形成覆盖导电接触的第二层介电材料，在覆盖导电接触的第二层中形成空隙区域，形成覆盖空隙区域的第三层电介质材料，以及在第三层中形成另一个空隙区域 覆盖第二层中的空隙区域的至少一部分。 该方法通过形成填充两个空隙区域以接触导电触点的导电材料而继续。