公开(公告)号：US07829466B2

公开(公告)日：2010-11-09

申请号：US12365300

申请日：2009-02-04

申请人： Frank S. Johnson ,  Richard T. Schultz

发明人： Frank S. Johnson ,  Richard T. Schultz

IPC分类号： H01L21/311

CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

摘要翻译： 提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。 这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。 侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。 通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

公开(公告)号：US20100197096A1

公开(公告)日：2010-08-05

申请号：US12365300

申请日：2009-02-04

申请人： Frank S. JOHNSON ,  Richard T. Schultz

发明人： Frank S. JOHNSON ,  Richard T. Schultz

IPC分类号： H01L21/336

CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

摘要翻译： 提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。 这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。 侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。 通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

公开(公告)号：US20120313148A1

公开(公告)日：2012-12-13

申请号：US13157411

申请日：2011-06-10

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/283 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/66545

摘要： A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

摘要翻译： 半导体器件制造工艺包括在半导体衬底上的一个或多个替代金属栅极上形成绝缘心轴。 心轴包括第一绝缘材料。 每个心轴具有与其底部浇口大致相同的宽度，每个心轴至少与其下面的浇口一样宽。 在每个绝缘心轴周围形成心轴间隔物。 心轴间隔件包括第一绝缘材料。 每个心轴间隔件具有从底部变宽到顶部较窄的轮廓。 第二绝缘材料的第二绝缘层形成在晶体管的上方。 通过从心轴之间的晶体管的部分去除第二绝缘材料来形成到栅极的源极和漏极的沟槽。 通过在第一沟槽中沉积导电材料来形成与栅极的源极和漏极的沟槽接触。

公开(公告)号：US20120025316A1

公开(公告)日：2012-02-02

申请号：US12848744

申请日：2010-08-02

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.

摘要翻译： 集成的鳍状场效应晶体管（FinFET）以及在浅沟槽隔离（STI）区域上具有EPI限定的鳍高度的体晶片上制造这种器件的方法。 FinFET通道覆盖半导体本体内的STI区域，而散热片延伸超出STI区域进入注入半导体本体的源极和漏极区域。 对于体源极和漏极区域，提供了减小的外部FinFET电阻，并且翅片延伸到体源极和漏极区域中，在传统的绝缘体上硅（SOI）器件上提​​供了改进的热性能。

公开(公告)号：US06671846B1

公开(公告)日：2003-12-30

申请号：US09684770

申请日：2000-10-06

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G01R3128

CPC分类号： G01R31/31835 ,  G01R31/318357 ,  G06F11/261 ,  G06F17/5022

摘要： Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. A different logic cone is derived for each of the multiple failing output signals at output pads. The convergence or intersection point of the multiple logic cones indicates the probable cause of faulty components of the circuit.

摘要翻译： 通过使用传统的仿真，原理图和波形查看工具自动识别，跟踪和显示电路的相关逻辑单元和波形。 导出到每个逻辑单元的输入和输出波形以及每个波形的转换和转换时间点。 输出波形和所选择的转换时间点识别预期输入波形及其在所选择的转换时间点引起输出信号转换的转换时间。 预测输入信号是前一预测逻辑单元的输出信号，由此识别先前的预测逻辑单元。 用每个新的识别的预测逻辑单元执行该过程的重复以自动导出单元的串联或逻辑锥。 对于输出焊盘处的多个故障输出信号中的每一个导出不同的逻辑锥。 多个逻辑锥的会聚或交点指示电路故障组件的可能原因。

公开(公告)号：US06653883B2

公开(公告)日：2003-11-25

申请号：US10210488

申请日：2002-07-31

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H03R300

CPC分类号： G06F1/10

摘要： A clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. When the tree deskew circuit is deskewed for a multilevel clock tree, the temporary clock net of that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals. After a predetermined number of adjustment cycles, the overall clock skew of the variable delay clock buffer signal is minimized by repeated adjustments. The variable delay clock buffer signals of each level may be optionally set as conditions warrant.

公开(公告)号：US08716124B2

公开(公告)日：2014-05-06

申请号：US13295574

申请日：2011-11-14

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/4763

CPC分类号： H01L27/088 ,  H01L21/76801 ,  H01L21/76895 ,  H01L21/76897

摘要： A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

摘要翻译： 半导体器件制造工艺包括在半导体衬底上的替代金属栅极上形成绝缘心轴，其中第一栅极具有源极和漏极，并且至少一个第二栅极与第一栅极隔离。 在每个绝缘心轴周围形成心轴间隔物。 心轴和心轴间隔件包括第一绝缘材料。 第二绝缘材料的第二绝缘层形成在晶体管的上方。 通过去除绝缘心轴之间的第二绝缘材料，将一个或多个第一沟槽形成到第一栅极的源极和漏极。 通过去除第二栅极上方的第一绝缘材料和第二绝缘材料的部分，形成第二沟槽到第二栅极。 第一沟槽和第二沟槽填充有导电材料，以形成第一栅极的源极和漏极的第一接触以及到第二栅极的第二接触。

公开(公告)号：US20100304564A1

公开(公告)日：2010-12-02

申请号：US12475796

申请日：2009-06-01

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475

摘要： A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.

摘要翻译： 半导体器件制造工艺包括使用硬掩模在半导体衬底上形成晶体管的栅极。 在门上的一个或多个选定区域中选择性地去除硬掩模。 在所选择的区域中去除硬掩模允许栅极通过位于晶体管基本上的至少一个绝缘层连接到上金属层。 导电材料沉积在通过至少一个绝缘层形成的一个或多个沟槽中。 导电材料在所选择的区域中的至少一个中形成与栅极的局部互连。

公开(公告)号：US20100301482A1

公开(公告)日：2010-12-02

申请号：US12475989

申请日：2009-06-01

申请人： Richard T. Schultz ,  Donald R. Weiss

发明人： Richard T. Schultz ,  Donald R. Weiss

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76895 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

摘要翻译： 通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。 实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电 材料以形成自对准局部互连。

公开(公告)号：US07829973B2

公开(公告)日：2010-11-09

申请号：US11843768

申请日：2007-08-23

申请人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

发明人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

IPC分类号： H01G4/40

CPC分类号： H01G4/40

摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

摘要翻译： 设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。 具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。 两个电容器设置在第一和第二导轨之间。 电阻器连接到第三导轨和两个电容器。 以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。 两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。 电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。