公开(公告)号：US4924141A

公开(公告)日：1990-05-08

申请号：US929691

申请日：1986-11-12

申请人： Fred R. Taubner ,  Richard L. Doucette ,  Gerald B. Fredrickson

发明人： Fred R. Taubner ,  Richard L. Doucette ,  Gerald B. Fredrickson

IPC分类号： H01J61/35

CPC分类号： H01J61/35

摘要： An improved fluorescent lamp is disclosed. The lamp of the present invention includes an envelope containing an ionizable medium including mercury and having electrodes located within the envelope; an aluminum oxide reflector layer on the inner surface of the envelope, and a phosphor layer disposed on the reflector layer. The aluminum oxide reflector layer comprises particles of high purity aluminum oxide having an average particle size greater than 0.5 micrometer and less than or equal to about 1 micrometer and having a surface area of about 4 to 6 meter.sup.2 /gram. The aluminum oxide reflector layer preferably includes at least 95 weight percent alpha-alumina. Preferred coating weights for the reflector layer are from about 8.8 to about 11.1 milligram/square centimeter.

摘要翻译： 公开了一种改进的荧光灯。 本发明的灯包括一个包含可包含汞的电离介质并具有位于封套内的电极的外壳; 在外壳的内表面上的氧化铝反射器层和设置在反射器层上的荧光体层。 氧化铝反射层包括平均粒度大于0.5微米且小于或等于约1微米并具有约4至6米2 /克表面积的高纯度氧化铝颗粒。 氧化铝反射层优选包含至少95重量％的α-氧化铝。 反射层的优选涂层重量为约8.8至约11.1毫克/平方厘米。

公开(公告)号：US4281258A

公开(公告)日：1981-07-28

申请号：US958255

申请日：1978-11-06

申请人： Richard L. Doucette

发明人： Richard L. Doucette

IPC分类号： H03K19/086 ,  H03K19/21 ,  H03K19/082 ,  H03K19/20

CPC分类号： H03K19/212

摘要： A high speed, low component count, exclusive NOR gate in one embodiment comprising two input transistors whose emitters are connected to the bases of a pair of cross-coupled transistors with the collectors of the latter being connected in common and forming the output of the gate so that the current flow through the emitter cross-coupled transistors is controlled by the base voltages of the two input transistors such that an exclusive NOR gate arrangement is provided. In another embodiment, a pair of Schottky diodes are disposed between the emitters of the input transistors and the cross-coupled emitter transistors to bias the bases of the latter and to change the input signal levels required.

摘要翻译： 一个实施例中的高速，低分量计数，异或门包括两个输入晶体管，其发射极连接到一对交叉耦合晶体管的基极，而后者的集电极共同连接并形成栅极的输出 使得通过发射极交叉耦合晶体管的电流被两个输入晶体管的基极电压控制，从而提供异或门配置。 在另一实施例中，一对肖特基二极管设置在输入晶体管的发射极和交叉耦合的发射极晶体管之间，以偏置后者的基极并改变所需的输入信号电平。

公开(公告)号：US4754173A

公开(公告)日：1988-06-28

申请号：US117387

申请日：1987-10-30

申请人： William H. Smith ,  Richard L. Doucette

发明人： William H. Smith ,  Richard L. Doucette

IPC分类号： H03K3/2885 ,  H03K19/086 ,  H03F3/45

CPC分类号： H03K19/0866 ,  H03K3/2885

摘要： A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

摘要翻译： 一种锁存电路，其包括输入逻辑网络，该输入逻辑网络包含以多个级别连接的发射极耦合逻辑开关装置，以对所接收的输入信号执行逻辑运算。 锁存电路由耦合到差分开关电路的差分时钟信号控制，差分开关电路连接到输入逻辑网络以形成另一个开关电平。 输出缓冲器连接到输入逻辑网络以产生所选逻辑电压电平的输出信号。 当差分时钟信号处于通过状态时，输入逻辑网络使能将输出信号发送到输出缓冲器。 当差分时钟信号处于锁存或保持状态时，禁止输入逻辑网络，并且在差分时钟信号变化的条件下，使反馈网络能够将信号保持在输出缓冲器中。

公开(公告)号：US4145623A

公开(公告)日：1979-03-20

申请号：US839342

申请日：1977-10-04

申请人： Richard L. Doucette

发明人： Richard L. Doucette

IPC分类号： H03K3/286 ,  H03K3/2885 ,  H03K3/289 ,  H03K3/36 ,  H03K19/086 ,  H03K19/08

CPC分类号： H03K3/2885 ,  H03K19/0863 ,  H03K3/289

摘要： An EFL D-type latch having both true and complement output with a data input transistor and a bistable storage cell comprising first and second transistors, at least one of which is multi-emitter, connected such that the true output is connected to the collector of the first transistor of the storage cell and the complement output is connected to the collector of the data input transistor and the second transistor of the storage cell to take advantage of the phase inversion of the latter transistors depending upon which one of these transistors has current flowing therethrough. Also described is an EFL type complement output circuit connected as a D-type master-slave flip-flop, an RS latch, and a JK master-slave flip-flop using an RS master latch and a D-type slave latch. Also disclosed is a toggle flip-flop implemented with a D-type flip-flop to complete an EFL type logic family.

摘要翻译： 具有数据输入晶体管的真和输出输出的EFL D型锁存器和双稳态存储单元，其包括第一和第二晶体管，其中至少一个是多发射极，使得真实输出连接到 存储单元的第一晶体管和补码输出端连接到数据输入晶体管的集电极和存储单元的第二晶体管，以利用这些晶体管中的哪一个具有电流流动的后一晶体管的相位反转 通过。 还描述了使用RS主锁存器和D型从锁存器作为D型主从触发器，RS锁存器和JK主从触发器连接的EFL型补码输出电路。 还公开了用D型触发器实现的用于完成EFL型逻辑系列的触发器。