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104 条记录 (耗时 0.044 秒)

    Apparatus and method for device timing compensation
    1.
    发明授权
    Apparatus and method for device timing compensation 有权
    器件定时补偿的装置和方法

    公开(公告)号：US06226754B1

    公开(公告)日：2001-05-01

    申请号：US09169687

    申请日：1998-10-09

    申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

    发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

    IPC分类号： G06F104

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.

    摘要翻译： 具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。 内存核心存储数据。 存储器接口连接到一组连接和存储器核心。 存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。 存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。 存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。

    Apparatus and method for bus timing compensation
    2.
    发明授权
    Apparatus and method for bus timing compensation 有权
    总线定时补偿的装置和方法

    公开(公告)号：US06226757B1

    公开(公告)日：2001-05-01

    申请号：US09169245

    申请日：1998-10-09

    申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    IPC分类号： G06F104

    CPC分类号： G06F13/4226

    摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

    摘要翻译： 一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。 主设备连接到通信总线和时钟线。 主设备选择性地向通信总线施加信号。 一组从设备连接到通信总线和时钟线。 一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。 每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。

    Memory device and system including a low power interface
    3.
    发明授权
    Memory device and system including a low power interface 有权
    存储器件和系统包括低功率接口

    公开(公告)号：US06378018B1

    公开(公告)日：2002-04-23

    申请号：US09169506

    申请日：1998-10-09

    申请人： Ely K. Tsern ,  Thomas J. Holman ,  Richard M. Barth ,  Andrew V. Anderson ,  Paul G. Davis ,  Craig E. Hampel ,  Donald C. Stark ,  Abhijit M. Abhyankar

    发明人： Ely K. Tsern ,  Thomas J. Holman ,  Richard M. Barth ,  Andrew V. Anderson ,  Paul G. Davis ,  Craig E. Hampel ,  Donald C. Stark ,  Abhijit M. Abhyankar

    IPC分类号： G06F1300

    CPC分类号： G06F13/4243 ,  G06F13/1694 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

    摘要翻译： 存储器系统包括具有高速通道和低速通道的互连结构。 具有接口电路的存储器件耦合到互连结构。 接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。 存储器件在低功率模式和高功率模式下工作。 存储器控制器耦合到互连结构的高速通道和低速通道。 存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。 存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。 存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。 存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。 存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。 存储器件可以各自包括用于解释编码器件识别字的解码器。 存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。