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    Memory device and system including a low power interface
    1.
    发明授权
    Memory device and system including a low power interface 有权
    存储器件和系统包括低功率接口

    公开(公告)号：US06378018B1

    公开(公告)日：2002-04-23

    申请号：US09169506

    申请日：1998-10-09

    申请人： Ely K. Tsern ,  Thomas J. Holman ,  Richard M. Barth ,  Andrew V. Anderson ,  Paul G. Davis ,  Craig E. Hampel ,  Donald C. Stark ,  Abhijit M. Abhyankar

    发明人： Ely K. Tsern ,  Thomas J. Holman ,  Richard M. Barth ,  Andrew V. Anderson ,  Paul G. Davis ,  Craig E. Hampel ,  Donald C. Stark ,  Abhijit M. Abhyankar

    IPC分类号： G06F1300

    CPC分类号： G06F13/4243 ,  G06F13/1694 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

    摘要翻译： 存储器系统包括具有高速通道和低速通道的互连结构。 具有接口电路的存储器件耦合到互连结构。 接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。 存储器件在低功率模式和高功率模式下工作。 存储器控制器耦合到互连结构的高速通道和低速通道。 存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。 存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。 存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。 存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。 存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。 存储器件可以各自包括用于解释编码器件识别字的解码器。 存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。

    Apparatus and method for bus timing compensation
    2.
    发明授权
    Apparatus and method for bus timing compensation 有权
    总线定时补偿的装置和方法

    公开(公告)号：US06226757B1

    公开(公告)日：2001-05-01

    申请号：US09169245

    申请日：1998-10-09

    申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    IPC分类号： G06F104

    CPC分类号： G06F13/4226

    摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

    摘要翻译： 一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。 主设备连接到通信总线和时钟线。 主设备选择性地向通信总线施加信号。 一组从设备连接到通信总线和时钟线。 一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。 每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。

    Bank state tracking method and device
    6.
    发明授权
    Bank state tracking method and device 失效
    银行状态跟踪方法和设备

    公开(公告)号：US6003111A

    公开(公告)日：1999-12-14

    申请号：US974320

    申请日：1997-11-19

    申请人： Thomas J. Holman ,  Andrew V. Anderson

    发明人： Thomas J. Holman ,  Andrew V. Anderson

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0215

    摘要： A mechanism for tracking the state of a plurality of memory banks in a memory device includes a register which has a plurality of bits, with each bit corresponding to one of the memory banks in the memory device. An open bank circuit has an output coupled to the register and is responsive to both a bank select signal which identifies a first memory bank and an open signal, to set a register bit associated with the first memory bank. A close bank circuit has an output coupled to the register and is responsive to the bank select signal which identifies a second memory bank as well as a close signal to reset the register bit associated with the second memory bank and any banks adjacent to the second memory bank.

    摘要翻译： 用于跟踪存储器件中的多个存储体的状态的机构包括具有多个位的寄存器，每个位对应于存储器件中的一个存储体。 开路组电路具有耦合到寄存器的输出，并响应识别第一存储体和开启信号的存储体选择信号，以设置与第一存储体相关联的寄存器位。 闭路电路具有耦合到寄存器的输出，并且响应于识别第二存储器组的存储体选择信号以及闭合信号以复位与第二存储体相关联的寄存器位和与第二存储器相邻的任何存储体 银行。

    Tracking memory page state
    7.
    发明授权
    Tracking memory page state 失效
    跟踪内存页面状态

    公开(公告)号：US06910109B2

    公开(公告)日：2005-06-21

    申请号：US09164088

    申请日：1998-09-30

    申请人： Thomas J. Holman ,  Andrew V. Anderson

    发明人： Thomas J. Holman ,  Andrew V. Anderson

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0215

    摘要： The present invention is a method and apparatus for tracking a state of a page of a memory device which has at least a dependent bank structure. A page entry table contains attribute entries of the page. An access control circuit generates access information and a command in response to a memory access. A tracking circuit is coupled to the page entry table and the access control circuit to update the attribute entries in the page entry table according to the command and the access information.

    摘要翻译： 本发明是用于跟踪具有至少依赖银行结构的存储器件的页面的状态的方法和装置。 页面条目表包含页面的属性条目。 访问控制电路响应于存储器访问产生访问信息和命令。 跟踪电路被耦合到页面条目表和访问控制电路，以根据命令和访问信息更新页面条目表中的属性条目。

    Method and apparatus for interfacing to a computer memory
    8.
    发明授权
    Method and apparatus for interfacing to a computer memory 有权
    用于连接到计算机存储器的方法和装置

    公开(公告)号：US06453393B1

    公开(公告)日：2002-09-17

    申请号：US09663918

    申请日：2000-09-18

    申请人： Thomas J. Holman ,  Andrew V. Anderson

    发明人： Thomas J. Holman ,  Andrew V. Anderson

    IPC分类号： G06F1200

    CPC分类号： G06F13/1694

    摘要： A memory system includes a primary memory interface, coupled to a primary device, adapted to receive memory requests from the primary device, and to transmit memory device independent requests based on the memory requests from the primary device. An external memory interface is coupled to at least one memory device via a memory interconnect. A memory independent interconnect, coupled to the primary memory interface and the external memory interface, is adapted to transport the memory device independent requests from the primary memory interface to the external memory interface.

    摘要翻译： 存储器系统包括耦合到主设备的主存储器接口，适于从主设备接收存储器请求，以及基于来自主设备的存储器请求来发送存储设备独立请求。 外部存储器接口经由存储器互连耦合到至少一个存储器件。 耦合到主存储器接口和外部存储器接口的独立于存储器的互连适于将存储器件独立的请求从主存储器接口传送到外部存储器接口。