公开(公告)号：US20160380626A1

公开(公告)日：2016-12-29

申请号：US15229312

申请日：2016-08-05

Applicant: Freescale Semiconductor, Inc.

Inventor： BRUCE M. GREEN ,  ENVER KRVAVAC ,  JOSEPH STAUDINGER

IPC: H03K17/16

CPC classification number: H03K17/165 ,  G06F1/3206 ,  H03K17/162

Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

公开(公告)号：US20140087550A1

公开(公告)日：2014-03-27

申请号：US14086545

申请日：2013-11-21

Applicant: FREESCALE SEMICONDUCTOR, INC

Inventor： BRUCE M. GREEN ,  HALDANE S. HENRY ,  CHUN-LI LIU ,  KAREN E. MOORE ,  MATTHIAS PASSLACK

IPC: H01L21/285 ,  H01L29/47

CPC classification number: H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract translation: 实施例包括制造具有低泄漏肖特基接触的半导体器件的方法。 实施例包括提供部分完成的半导体器件，其包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US20160343809A1

公开(公告)日：2016-11-24

申请号：US14719999

申请日：2015-05-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： BRUCE M. GREEN ,  JENN HWA HUANG ,  VIKAS S. SHILIMKAR

IPC: H01L29/20 ,  H01L29/06 ,  H01L29/205 ,  H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L23/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/30621 ,  H01L21/76224 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L29/0657 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6605

Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.

Abstract translation: 器件的实施例包括半导体衬底，形成在第一衬底表面处的晶体管，形成在第一衬底表面上并电耦合到晶体管的第一导电特征，以及仅覆盖第二衬底表面的一部分的第二导电特征 以限定第一无导体区域。 在第一无导体区域内与第一导电特征垂直对准的空腔延伸到半导体衬底中。 电介质可以设置在空腔内并具有小于半导体衬底的介电常数的介电常数。 用于形成器件的方法可以包括形成半导体衬底，在半导体衬底上形成晶体管，形成第一导电特征，形成第二导电特征，形成无导体区域，形成腔体，以及填充腔体 电介质。