Abstract:
Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract:
An adjustable power splitter includes: a power divider with an input and a plurality, N, of divider outputs; a plurality, N, of adjustable phase shifters and a plurality, N, of adjustable attenuators series coupled to the divider outputs and providing a plurality, N, of power outputs; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the adjustable phase shifters and attenuation levels to be applied by the adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the adjustable phase shifters and the adjustable attenuators.
Abstract:
Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract:
Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
Abstract:
An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
Abstract:
An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.
Abstract:
Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.
Abstract:
The embodiments described herein provide inverse class F (class F−1) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier.
Abstract:
An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at a first voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at a different second voltage level. Finally, when the SMPA branch receives a different third combination of drive signals, it produces the output signal at a voltage level of substantially zero. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.
Abstract:
An embodiment of an amplifier includes N (N>1) switch-mode power amplifier (SMPA) branches. Each SMPA branch includes two drive signal inputs and one SMPA branch output. A module coupled to the amplifier samples an input RF signal, and produces combinations of drive signals based on the samples. When an SMPA branch receives a first combination of drive signals, it produces an output signal at one voltage level. Conversely, when the SMPA branch receives a different second combination of drive signals, it produces the output signal at another voltage level. At least two of the SMPA branches produce output signals having different absolute magnitudes. A combiner combines the output signals from all of the SMPA branches to produce a combined output signal that may have, at any given time, one of 2*N+1 quantization states.