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公开(公告)号：US20180123520A1
公开(公告)日：2018-05-03
申请号：US15342637
申请日：2016-11-03
Applicant: Freescale Semiconductor, Inc.
Inventor： Margaret A. Szymanowski , Ramanujam Srinidhi Embar , Roy Mclaren
CPC classification number: H03F1/0288 , H01L21/4825 , H03F1/3247 , H03F1/56 , H03F3/19 , H03F3/211 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2203/21103 , H03F2203/21106 , H03F2203/21142
Abstract: An amplifier includes first, second, and third inputs to receive an RF signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. The pair of phase adjustment paths are configured to adjust a phase of the RF signal differently for the first output.
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公开(公告)号：US09628027B2
公开(公告)日：2017-04-18
申请号：US14211410
申请日：2014-03-14
Applicant: Freescale Semiconductor, Inc.
Inventor： Ramanujam Srinidhi Embar , Damon G. Holmes , Joseph Staudinger
CPC classification number: H03F1/0288 , H01L23/645 , H01L23/66 , H01L24/48 , H01L2223/6611 , H01L2224/48227 , H01L2924/19107 , H03F1/0294 , H03F3/195 , H03F3/245 , H03F3/68 , H03F2200/451 , H03F2200/537 , H03F2200/541 , Y10T29/41 , H01L2924/00014 , H01L2224/45099
Abstract: The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. The multi-path integrated device includes a first output and a second output. The first output is configured to be coupled to a first output lead through a first bonding wire, and the second output is configured to be coupled to a second output lead through a second bonding wire. Due to their proximity, the second bonding wire has a first mutual inductance with the first bonding wire. A first compensation network is coupled to the first output, and a second compensation network is coupled to the second output. The second compensation network is configured to have a second mutual inductance with the first compensation network. The second mutual inductance at least partially cancels the effects of the first mutual inductance.
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Patent Agency Ranking
公开(公告)号：US10211784B2
公开(公告)日：2019-02-19
申请号：US15342637
申请日：2016-11-03
Applicant: Freescale Semiconductor, Inc.
Inventor： Margaret A. Szymanowski , Ramanujam Srinidhi Embar , Roy Mclaren
Abstract: An amplifier includes first, second, and third inputs to receive an RF signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. The pair of phase adjustment paths are configured to adjust a phase of the RF signal differently for the first output.
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公开(公告)号：US20170250656A1
公开(公告)日：2017-08-31
申请号：US15055330
申请日：2016-02-26
Applicant: Freescale Semiconductor, Inc.
Inventor： Sarmad K. Musa , Ramanujam Srinidhi Embar
CPC classification number: H03F1/0288 , H01P5/12 , H03F1/07 , H03F3/19 , H03F3/211 , H03F2200/451 , H03F2203/21142
Abstract: A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal carried by the first signal conduction path. A delay element is configured to impose a phase delay on the output signal of the first coupler to generate a delayed output signal. The device includes a second coupler coupled to the second signal conduction path. The second coupler is connected to the delay element and configured to inject the delayed output signal into the second signal conduction path.
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公开(公告)号：US09647611B1
公开(公告)日：2017-05-09
申请号：US14925718
申请日：2015-10-28
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Ramanujam Srinidhi Embar , Joseph Staudinger , Margaret A. Szymanowski
CPC classification number: H03F1/0288 , H03F3/195 , H03F3/245 , H03F2200/192 , H03F2200/204 , H03F2200/411 , H03F2200/451 , H03F2200/534
Abstract: A reconfigurable Doherty power amplifier includes a packaged power splitter device, main and peaking amplifiers, and a combiner circuit. The power splitter device includes a power divider, input terminals coupled to first and second ports of the power divider, and output terminals coupled to third and fourth ports of the power divider. One of the input terminals is coupled to an RF signal input terminal, and the other input terminal is terminated. The power divider receives an input RF signal, and produces main and peaking RF signals at the third and fourth ports of the power divider, respectively. The main and peaking amplifiers amplify the main and peaking RF signals, respectively. The combiner circuit includes a summing node and a phase delay element between outputs of the main and peaking amplifiers. An RF signal output terminal is coupled to the summing node.
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公开(公告)号：US09634615B1
公开(公告)日：2017-04-25
申请号：US15064058
申请日：2016-03-08
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Abdulrhman M. S. Ahmed , Ramanujam Srinidhi Embar , Yu-Ting D. Wu
CPC classification number: H03F1/0288 , H03F3/19 , H03F3/211 , H03F3/245 , H03F2200/111 , H03F2200/225 , H03F2200/451 , H03F2203/21103 , H03F2203/21139 , H03F2203/21142
Abstract: A Doherty amplifier device operable over multiple frequency bands includes a controller that, in some embodiments, is configured to output a carrier bias signal to a first amplifier and a peaking bias signal to a second amplifier as part of a first operating configuration associated with a first frequency band, and output the peaking bias signal to the second amplifier and the carrier bias signal to a third amplifier as part of a second operating configuration associated with a second frequency band. In some embodiments, the controller is configured to select an impedance inverter configuration associated with a respective frequency band. At least one impedance inverter configuration includes a compound impedance inverter including two or more impedance inverters coupled in series with at least one node between the two or more impedance inverters coupled to an output of a third amplifier.
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公开(公告)号：US09831835B2
公开(公告)日：2017-11-28
申请号：US15055330
申请日：2016-02-26
Applicant: Freescale Semiconductor, Inc.
Inventor： Sarmad K. Musa , Ramanujam Srinidhi Embar
CPC classification number: H03F1/0288 , H01P5/12 , H03F1/07 , H03F3/19 , H03F3/211 , H03F2200/451 , H03F2203/21142
Abstract: A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal carried by the first signal conduction path. A delay element is configured to impose a phase delay on the output signal of the first coupler to generate a delayed output signal. The device includes a second coupler coupled to the second signal conduction path. The second coupler is connected to the delay element and configured to inject the delayed output signal into the second signal conduction path.
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